TECHNIQUES FOR MAPPING DEVICE ADDRESSES TO PHYSICAL MEMORY ADDRESSES

• US 20120272037A1
• Filed: 04/21/2012
• Published: 10/25/2012
• Est. Priority Date: 04/21/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nguyen, Hoang-Nam, Raisch, Christoph, Themann, Jan-Bernd, Hering, Hannes, Bayer, Gerd
• Granted Patent: US 9,355,031 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/656 Address space sharing

Abstract

A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component interconnect (PCI) device coupled to the IOMMU, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage. The mapper is configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space. The IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage.

Claims

1. A data processing system, comprising:

a main storage;

an input/output memory management unit (IOMMU) coupled to the main storage;

a peripheral component interconnect (PCI) device coupled to the IOMMU, wherein the system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage; and

a mapper configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space, wherein the IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage.

2. The data processing system of claim 1, wherein the mapper is included within an operating system of the data processing system or a PCI device driver associated with the PCI device.

3. The data processing system of claim 1, wherein the data processing system is configured to allocate the physical memory in the main storage in memory blocks.

4. The data processing system of claim 3, wherein the memory blocks have different block sizes.

5. The data processing system of claim 1, wherein the data processing system is configured to apply a block size with a power of two.

6. The data processing system of claim 5, wherein the block size is 4 kB.

7. The data processing system of claim 5, wherein the IOMMU is configured to translate the PCI address to the physical memory address by combining a first address part of the PCI address referring to a memory block of the physical memory address and a second address part of the PCI address referring to a memory unit within the memory block.

8. The data processing system of claim 1, wherein the PCI device is configured to internally use a device memory address and includes a mapping unit that is configured to translate the device memory address to the PCI address.

9. The data processing system of claim 8, wherein the PCI device is configured to provide internal individual memory areas to be addressed by the device memory address and the mapping unit has a key assigned to each individual memory area and is configured only to translate the device memory address into the PCI address if the device memory address is provided with the key assigned to the memory area that includes the device memory address.

10. The data processing system of claim 9, wherein the mapping unit is configured to translate the device memory address to the PCI address by adding an offset to the device memory address.

11. The data processing system of claim 10, wherein the offset depends on the key.

12. The data processing system of claim 10, wherein the mapping unit is configured to map the device memory address to the PCI address under application of bit-shifting of the device memory address according to a power of a given block size.

13. The data processing system of claim 8, wherein a PCI device driver associated with the PCI device is configured to setup the mapping unit.

14. The data processing system of claim 1, wherein the mapper is configured to allocate separate contiguous areas of PCI memory within the contiguous PCI address space for application requests, and wherein the separate areas are provided within the contiguous PCI address space spaced apart from each other.

15. The data processing system of claim 1, wherein the PCI device is configured to provide the PCI address to the IOMMU together with a resource identifier identifying the PCI device.

16. A data processing system, comprising:

an input/output memory management unit (IOMMU) coupled to a main storage;

a peripheral component interconnect (PCI) device coupled to the IOMMU, wherein the system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage; and

a mapper configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space, wherein the mapper is configured to allocate separate contiguous areas of PCI memory within the contiguous PCI address space for application requests, and wherein the IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage.

17. The data processing system of claim 16, wherein the PCI device is configured to internally use a device memory address and includes a mapping unit that is configured to translate the device memory address to the PCI address.

18. The data processing system of claim 17, wherein the PCI device is configured to provide internal individual memory areas to be addressed by the device memory address and the mapping unit has a key assigned to each individual memory area and is configured only to translate the device memory address into the PCI address if the device memory address is provided with the key assigned to the memory area that includes the device memory address.

19. A method of accessing physical memory, comprising:

mapping, using an input/output memory management unit (IOMMU), a peripheral component interconnect (PCI) address from a PCI device to a physical memory address within main storage;

mapping, using a mapper, between an allocated amount of physical memory of the main storage and a contiguous PCI address space; and

translating, using the IOMMU, PCI addresses of the contiguous PCI address space to a physical memory address within the main storage.

20. The method of claim 19, wherein the PCI device is configured to internally use a device memory address and the method further comprises:

translating, using a mapping unit of the PCI device, the device memory address to the PCI address.