INTERFACE

• US 20120272089A1
• Filed: 12/17/2010
• Published: 10/25/2012
• Est. Priority Date: 12/17/2009
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Hatfield, Robert James, Mcleod, Gordon Richard, Pennock, John Laurence
• Granted Patent: US 9,378,176 B2
• Time in Patent Office: Days
• US Class Current: 713/501
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: H04J 3/00 Time-division multiplex systems H04J14/00 takes precedence; relay systems H04B7/14; selecting techniques H04Q
• CPC Class Codes: H04J 3/16 in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted H04J3/17, H04J3/24 take precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention relates to methods and apparatus for data transfer. A data interface is described with at least a first data terminal for either outputting or receiving a data signal. In bi-directional embodiments there may be one terminal for receiving data and one terminal for outputting data. A bit clock terminal outputs or receives a bit clock signal; and a frame clock terminal for outputs or receives a frame clock signal. Interface control circuitry is configurable to associate data outputted or received in each frame with time slots (1-8) of a predetermined number of bits (x, y, z) wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame.

Claims

1. A data interface comprising:

a first data terminal for outputting or receiving a data signal;

a bit clock terminal for outputting or receiving a bit clock signal;

a frame clock terminal for outputting or receiving a frame clock signal; and

control circuitry configurable to associate data outputted or received in each frame with time slots of a predetermined number of bits;

wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame.

2. A data interface as claimed in claim 1 wherein the control circuitry is configurable to associate predetermined time slots with predetermined data channels and to access the relevant channel only if the frame contains the appropriate time slot.

3. A data interface as claimed in claim 2 wherein the control circuitry is configurable to control which time slots are associated with each data channel.

4. A data interface as claimed in claim 1 wherein the control circuitry is configurable to control the number of bits associated with each time slot.

5. A data interface as claimed in claim 1 wherein the control circuitry is configurable such that a plurality of classes of data flow may be output or received within a frame time defined by the frame clock signal, each class of data flow being associated with a group of time slots, each group of time slots comprising one or more time slots.

6. A data interface as claimed in claim 5 wherein the control circuitry is configured so as to apply different handling to data associated with each class of data flow.

7. A data interface as claimed in claim 5 wherein a configurable maximum number of contiguous time slots is associated with each said group of time slots associated with a class of data flow.

8. A data interface as claimed in claim 5 wherein the control circuitry is configurable to control the order in which said groups of time slots associated with classes of data flow appear in a frame.

9. A data interface as claimed in claim 5 wherein at least one class of data flow comprises an application data flow of application data.

10. A data interface as claimed in claim 9 wherein a configurable number of time slots may be associated with one or more application data channels.

12. A data interface as claimed claim 9 wherein at least one said application data channel comprises an audio data channel or a haptic data channel.

14. A data interface as claimed in claim 5 wherein at least one class of data flow comprises a control data flow of control data and wherein a configurable number of time slots may be associated with at least one control channel for transmitting or receiving control data.

16. A data interface as claimed in claim 14 wherein at least one said control channel is associated with an intermittent low bandwidth data flow.

17. A data interface as claimed in claim 14 wherein at least one control channel comprises a channel for control data for configuring the interface or for control data for operational configuration of circuitry coupled to the interface.

20. A data interface as claimed in claim 14 wherein at least one said control channel comprises a channel for data indicating a selected haptic waveform.

22. A data interface as claimed in claim 5 wherein at least one class of data flow comprises an program data flow of program data wherein a configurable number of time slots may be associated with at least one programming channel for outputting or receiving programming data.

29. A data interface as claimed in any of claim 5 wherein at least one class of data flow comprises a haptic data flow of haptic data.

30. A data interface as claimed in claim 5 wherein the control circuitry is configured such that a configurable number of time slots are associated with application data, a configurable number of time slots are associated with control data and a configurable number of time slots are associated with program data wherein any time slots associated with control data occur after any time slots associated with application data and where any time slots associated with program data occur after any time slots associated with control data.

40. A data interface as claimed in claim 5 wherein the control circuitry is configured such that the frequency of the frame clock signal can be changed at any time.

41. An integrated circuit comprising at least one data interface as claimed in claim 5.

43. An electronic device comprising a first and second integrated circuits, wherein a first data interface of the first integrated circuit is connected to a second data interface of the second integrated circuit and wherein at least one of the first and second data interfaces comprises a data interface as claimed in claim 5.

44. As electronic device as claimed in claim 43 wherein said electronic device is at least one of:

a battery powered device, a portable device, a personal audio device, a personal video device;

a mobile telephone, a personal data assistant, a gaming device, a portable computing device, a laptop and a satellite navigation system.

11. (canceled)

13. (canceled)

15. (canceled)

18. (canceled)

19. (canceled)

21. (canceled)

23-28. -28. (canceled)

31-39. -39. (canceled)

42. (canceled)

45. A method of data transfer comprising:

receiving a bit clock signal;

receiving a frame clock signal;

transmitting or receiving a data signal wherein said data is transmitted or received in one or more time slots of a predetermined number of bits;

wherein the bit clock signal frequency may be varied at any time independently of the frame clock so as to vary the number of time slots in a frame.

46-53. -53. (canceled)

54. A method of data transfer comprising:

defining a frame period via a frame clock signal;

defining a frame format comprising a plurality of time slots, wherein each time slot is of a predetermined number of bits and is associated with a specified data channel; and

setting a bit clock rate so as to include a desired number of time slots.

55. (canceled)

56. A data interface having control circuitry responsive to a bit clock signal and a frame clock signal to transfer data wherein the frequency of the bit clock signal is variable independently of the frame clock signal.

57. A data transfer protocol comprising:

accessing a frame format mapping defining a plurality of time slots, wherein each time comprises a defined number of bit and is associated with a specified data channel; and

transferring data, at a bit rate defined by a bit clock signal, in said time slots in order from the beginning of a frame period to the end of a frame period;

wherein the frequency of the bit clock signal can be changed to alter the number of time slots in a frame.

58. (canceled)

59. (canceled)

60. A data interface comprising a data terminal for outputting or receiving data wherein said interface can output or receive a plurality of different data types in a single frame period.

61-64. -64. (canceled)