SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20120273779A1
• Filed: 07/11/2012
• Published: 11/01/2012
• Est. Priority Date: 07/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, MIYAIRI, Hidekazu, AKIMOTO, Kengo, SHIRAISHI, Kojiro
• Granted Patent: US 8,841,710 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/10 OLED displays
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/8722 : Peripheral sealing arrangements, e.g. adhesives, sealants

Abstract

In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate having an insulating surface;

a first insulating film over the gate electrode;

an oxide semiconductor layer over the first insulating film;

a second insulating film over the oxide semiconductor layer; and

a conductive film over the oxide semiconductor layer,

wherein a first region in which the oxide semiconductor layer and the second insulating film are in contact with each other and overlap with at least part of the gate electrode, and

wherein a thickness of the oxide semiconductor layer in a second region in which the oxide semiconductor layer and the conductive film are in contact with each other is smaller than a thickness of the oxide semiconductor layer in the first region.

2. The semiconductor device according to claim 1, wherein part of the conductive film is formed over the second insulating film.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least In, Ga and Zn.

4. The semiconductor device according to claim 1, wherein the first insulating film is one of a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an aluminum nitride film and an yttrium oxide film.

5. The semiconductor device according to claim 1, wherein the second insulating film is one of a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an aluminum nitride film and an yttrium oxide film.

6. The semiconductor device according to claim 1, wherein the first insulating film includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

7. The semiconductor device according to claim 1, wherein the second insulating film includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

8. The semiconductor device according to claim 1, wherein the conductive film is a stacked film including a titanium film and an aluminum film.

9. The semiconductor device according to claim 1, further comprising a silicon nitride film or a silicon nitride oxide film between the gate electrode and the first insulating film.

10. A semiconductor device comprising:

a gate electrode over a substrate;

a first insulating layer over the gate electrode, the first insulating layer comprising silicon nitride;

a second insulating layer over the first insulating layer, the second insulating layer comprising silicon oxide;

an oxide semiconductor layer comprising indium, over the gate electrode with the first insulating layer and the second insulating layer interposed therebetween;

a source electrode and a drain electrode over the oxide semiconductor layer;

a third insulating layer over the source and drain electrodes, the third insulating layer comprising silicon oxide;

a fourth insulating layer over the third insulating layer, the fourth insulating layer comprising silicon nitride;

a fifth insulating layer over the fourth insulating layer, the fifth insulating layer comprising an organic material; and

a pixel electrode over the fifth insulating layer.

11. The semiconductor device according to claim 10, wherein the second insulating layer is in contact with the third insulating layer.

12. The semiconductor device according to claim 10, wherein the oxide semiconductor layer includes at least indium, gallium and zinc.

13. The semiconductor device according to claim 10, wherein the first insulating layer includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

14. The semiconductor device according to claim 10, wherein the substrate is a glass substrate.

15. The semiconductor device according to claim 10, wherein the fifth insulating layer comprises acrylic.

16. The semiconductor device according to claim 10, further comprising an FPC connected to the substrate.

17. A semiconductor device comprising:

a gate electrode over a substrate;

a first insulating layer over the gate electrode, the first insulating layer comprising silicon nitride;

a second insulating layer over the first insulating layer, the second insulating layer comprising silicon oxide;

an oxide semiconductor layer comprising indium, over the gate electrode with the first insulating layer and the second insulating layer interposed therebetween;

a source electrode and a drain electrode over the oxide semiconductor layer;

a third insulating layer over the source and drain electrodes, the third insulating layer comprising silicon oxide;

a fourth insulating layer over the third insulating layer, the fourth insulating layer comprising silicon nitride,

a fifth insulating layer over the fourth insulating layer, the fifth insulating layer comprising an organic material; and

a pixel electrode over the fifth insulating layer,

wherein the gate electrode comprises copper.

18. The semiconductor device according to claim 17, wherein the second insulating layer is in contact with the third insulating layer.

19. The semiconductor device according to claim 17, wherein the oxide semiconductor layer includes at least indium, gallium and zinc.

20. The semiconductor device according to claim 17, wherein the first insulating layer includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

21. The semiconductor device according to claim 17, wherein the substrate is a glass substrate.

22. The semiconductor device according to claim 17, wherein the fifth insulating layer comprises acrylic.

23. The semiconductor device according to claim 17, further comprising an FPC connected to the substrate.

24. A semiconductor device comprising:

a gate electrode over a substrate;

a first insulating layer over the gate electrode, the first insulating layer comprising silicon nitride;

a second insulating layer over the first insulating layer, the second insulating layer comprising silicon oxide;

an oxide semiconductor layer comprising indium, over the gate electrode with the first insulating layer and the second insulating layer interposed therebetween;

a third insulating layer on and in contact with the oxide semiconductor layer, the third insulating layer comprising silicon oxide;

a source electrode and a drain electrode over the oxide semiconductor layer and the third insulating layer;

a fourth insulating layer over the third insulating layer and the source and drain electrodes, the fourth insulating layer comprising silicon nitride,

a fifth insulating layer over the fourth insulating layer, the fifth insulating layer comprising an organic material; and

a pixel electrode over the fifth insulating layer.

25. The semiconductor device according to claim 24, wherein the oxide semiconductor layer includes at least indium, gallium and zinc.

26. The semiconductor device according to claim 24, wherein a thickness of the oxide semiconductor layer in a first region in which the oxide semiconductor layer and the source and drain electrodes are in contact with each other is smaller than a thickness of the oxide semiconductor layer in a second region in which the oxide semiconductor layer and the third insulating layer are in contact with each other.

27. The semiconductor device according to claim 24, the semiconductor device further comprising a sixth insulating layer between the third insulating layer and the fourth insulating layer,

wherein the sixth insulating layer comprises silicon oxide.

28. The semiconductor device according to claim 27, wherein the second insulating layer is in contact with the sixth insulating layer.

29. The semiconductor device according to claim 24, wherein the first insulating layer includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

30. The semiconductor device according to claim 24, wherein the substrate is a glass substrate.

31. The semiconductor device according to claim 24, wherein the fifth insulating layer comprises acrylic.

32. The semiconductor device according to claim 24, further comprising an FPC connected to the substrate.

33. A semiconductor device comprising:

a gate electrode over a substrate;

a first insulating layer over the gate electrode, the first insulating layer comprising a silicon nitride layer;

a second insulating layer over the first insulating layer, the second insulating layer comprising a silicon oxide layer;

an oxide semiconductor layer comprising indium, over the gate electrode with the first insulating layer and the second insulating layer interposed therebetween;

a source electrode and a drain electrode over the oxide semiconductor layer and the third insulating layer;

a third insulating layer on and in contact with the oxide semiconductor layer, the third insulating layer comprising a silicon oxide layer;

a fourth insulating layer over the third insulating layer and the source and drain electrodes, the fourth insulating layer comprising a silicon nitride layer,

a fifth insulating layer over the fourth insulating layer, the fifth insulating layer comprising an organic material; and

a pixel electrode over the fifth insulating layer,

wherein the gate electrode comprises copper.

34. The semiconductor device according to claim 33, wherein the oxide semiconductor layer includes at least indium, gallium and zinc.

35. The semiconductor device according to claim 33, wherein a thickness of the oxide semiconductor layer in a first region in which the oxide semiconductor layer and the source and drain electrodes are in contact with each other is smaller than a thickness of the oxide semiconductor layer in a second region in which the oxide semiconductor layer and the third insulating layer are in contact with each other.

36. The semiconductor device according to claim 33, the semiconductor device further comprising a sixth insulating layer between the third insulating layer and the fourth insulating layer,

wherein the sixth insulating layer comprises silicon oxide.

37. The semiconductor device according to claim 36, wherein the second insulating layer is in contact with the third insulating layer.

38. The semiconductor device according to claim 33, wherein the first insulating layer includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

39. The semiconductor device according to claim 33, wherein the substrate is a glass substrate.

40. The semiconductor device according to claim 33, wherein the fifth insulating layer comprises acrylic.

41. The semiconductor device according to claim 33, further comprising an FPC connected to the substrate.

42. A semiconductor device comprising:

a gate electrode over a substrate;

an oxide semiconductor layer comprising indium,

a first insulating layer and a second insulating layer between the gate electrode and the oxide semiconductor layer;

a third insulating layer and a fourth insulating layer adjacent to the oxide semiconductor layer,

a fifth insulating layer comprising an organic material over the gate electrode, the oxide semiconductor layer, and the first insulating layer to the fourth insulating layer; and

a pixel electrode over the fifth insulating layer,

wherein the second insulating layer is provided between the gate electrode and the first insulating layer,

wherein the third insulating layer is provided between the oxide semiconductor layer and the fourth insulating layer;

wherein each of the first insulating layer and the third insulating layer comprises silicon oxide; and

wherein each of the second insulating layer and the fourth insulating layer comprises silicon nitride.

43. The semiconductor device according to claim 42, wherein the first insulating layer is in contact with the third insulating layer.

44. The semiconductor device according to claim 42, wherein the oxide semiconductor layer includes at least indium, gallium and zinc.

45. The semiconductor device according to claim 42, further comprising a source electrode and a drain electrode,

wherein the source electrode and the drain electrode are on and in contact with the oxide semiconductor layer.

46. The semiconductor device according to claim 42, wherein the gate electrode comprises copper.

47. The semiconductor device according to claim 42, wherein the first insulating layer includes a halogen element, and the concentration of the halogen element is from 1×

10¹⁵ cm<sup>−

3</sup> to 1×

10²⁰ cm<sup>−

3</sup>.

48. The semiconductor device according to claim 42, wherein the substrate is a glass substrate.

49. The semiconductor device according to claim 42, wherein the fifth insulating layer comprises acrylic.

50. The semiconductor device according to claim 42, further comprising an FPC connected to the substrate.