SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20120273850A1
• Filed: 01/10/2012
• Published: 11/01/2012
• Est. Priority Date: 04/29/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: CHUN, Sung Kil
• Granted Patent: US 8,435,847 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A semiconductor device and a method for fabricating the same are disclosed. A fin of the semiconductor device including a fin-shaped channel region is configured in the form of a non-uniform structure, and a leakage current caused by the electric field effect generated in the semiconductor device is prevented from being generated, resulting in an increased operation stability of the semiconductor device.

Claims

1. A method for fabricating a semiconductor device comprising:

providing a substrate having an active region and a device isolation film;

forming an ion implantation region within the active region; and

etching the active region until the ion implantation region is at least partly etched to define a fin-shaped structure, the fin-shaped structure having a non-uniform upper surface that increases a channel length of a gate associated with the fin-shaped structure.

2. The method of claim 1, wherein the upper surface of the fin-shaped structure has a center section that is at lower level than an outer edge of the upper surface of the fin-shaped structure.

3. The method according to claim 1, wherein the fin-shaped structure includes a saddle-fin structure that has a concave upper surface.

4. The method according to claim 1, wherein a difference in height between the center section of the upper surface of the fin-shaped structure and the outer edge part of the upper surface of the fin-shaped structure is 20% or higher of a width of the fin-shaped structure.

5. The method according to claim 1, wherein the device isolation film is etched with the active region during the etch step, the device isolation film being etched more than the active region.

6. The method according to claim 1, further comprising:

forming a gate insulation film and a gate pattern over the fin-shaped structure.

7. The method according to claim 6, further comprising:

forming a source/drain region by implanting ions in the active region adjacent to the gate patterns.

8. The method according to claim 6, wherein the gate pattern includes polysilicon.

9. The method according to claim 6, further comprising:

forming a buried gate pattern by etching back the gate pattern and the gate insulation film.

10. A method for forming a semiconductor device comprising:

forming a device isolation film defining an active region over a semiconductor substrate;

forming a hard mask pattern over the active region and the device isolation film;

etching the active region using a first etch step to form a first recess in the active region using the hard mask pattern as an etch mask; and

etching a lower part of the first recess using a second etch step, wherein a center section of a top surface of the fin-shaped active region is formed to be lower in height than an outer edge part of the top surface of the fin-shaped active region.

11. The method according to claim 10, wherein the fin-shaped active region includes a saddle-fin structure.

12. The method according to claim 10, wherein a difference in height between the center section of the top surface of the fin-shaped active region and the outer edge part of the top surface of the fin-shaped active region is at least 20% of a width of the fin-shaped active region.

13. The method according to claim 10, wherein the first etch step uses an anisotropic etching method, and the second etch step uses an isotropic etching method.

14. The method according to claim 10, wherein the active region and the device isolation film are etched together during the first etch step, the device isolation film being etched more than the active region during the first etch step.

15. A semiconductor device, comprising:

a substrate an active region and a device isolation film having an upper surface;

a recess being provided in the active region and having a bottom surface that is at a higher level than the upper surface of the device isolation film, the bottom surface of the recess being non-uniform; and

a gate structure formed over the non-uniform bottom surface of the recess.

16. The device of claim 15, wherein the bottom surface of the recess defines a non-uniform upper surface of a fin-shaped active region.

17. The device of claim 16, wherein the active region extends along a first direction and the gate structure extends along a second direction different than the first direction,

wherein the non-uniform upper surface of the fin-shaped active region has a concave shape.