SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

• US 20120273930A1
• Filed: 04/26/2012
• Published: 11/01/2012
• Est. Priority Date: 04/27/2011
• Status: Active Grant

• Current Assignee: Unimicron Technology Corporation
• Original Assignee: Unimicron Technology Corporation
• Inventors: Tseng, Tzyy-Jang, Hu, Dyi-Chung, Hu, Yu-Shan
• Granted Patent: US 8,624,366 B2
• Time in Patent Office: Days
• US Class Current: 257/675
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Claims

1. A semiconductor package structure, comprising:

a semiconductor chip having an active surface and an opposite inactive surface, a plurality of electrode pads formed on the active surface, and a plurality of metal bumps disposed on the electrode pads, respectively;

an encapsulant encapsulating the semiconductor chip, with the active surface of the semiconductor chip being exposed therefrom;

a dielectric layer formed on the active surface of the semiconductor chip and the encapsulant and having a plurality of patterned intaglios for exposing the metal bumps;

a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps, wherein the wiring layer extends to an area greater than the active surface of the semiconductor chip by means of the presence of the encapsulant and the dielectric layer;

an insulating protective layer formed on the dielectric layer and the wiring layer and having a plurality of openings for exposing portions of the wiring layer; and

a metal foil having a plurality of metal posts disposed on a surface thereof, wherein the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip, thereby effectively dissipating heat generated by the semiconductor chip to the ambient.

2. The structure of claim 1, further comprising a cap layer formed on a top surface of the metal foil.

3. The structure of claim 2, wherein the cap layer is made of an insulating material or a metallic material.

4. The structure of claim 1, further comprising a plurality of solder balls disposed on the portions of the wiring layer exposed from the openings of the insulating protective layer.

5. The structure of claim 1, further comprising a buffer layer formed on the active surface of the semiconductor chip.

6. A fabrication method of a semiconductor package structure, comprising:

providing a carrier board having a first adhesive layer formed on a surface thereof, and, a plurality of semiconductor chips, each of which has an active surface and an opposite inactive surface, a plurality of electrode pads formed on the active surface, and a plurality of metal bumps disposed on the electrode pads, respectively;

adhering the semiconductor chips to the first adhesive layer through the active surfaces thereof;

forming an encapsulant on the first adhesive layer to encapsulate the semiconductor chips;

providing a metal foil having a plurality of metal posts disposed on a surface thereof, and attaching the metal foil to the encapsulant through the surface thereof such that the metal posts penetrate the encapsulant and extend to the inactive surfaces of the semiconductor chips;

removing the carrier board and the first adhesive layer;

forming a dielectric layer on the encapsulant and the semiconductor chips, wherein the dielectric layer has a plurality of patterned intaglios for exposing the metal bumps, respectively;

forming a wiring layer in the patterned intaglios of the dielectric layer such that the wiring layer is electrically connected to the metal bumps;

forming an insulating protective layer on the dielectric layer and the wiring layer, wherein the insulating protective layer has a plurality of openings for exposing portions of the wiring layer;

removing portions of the metal foil to form dicing lines such that the metal foil is separated corresponding to the semiconductor chips; and

cutting the encapsulant, the dielectric layer and the insulating protective layer along the dicing lines of the metal foil such that a plurality of semiconductor package structures are formed.

7. The method of claim 6, further comprising forming a cap layer on the metal foil after removing the carrier and the first adhesive layer, wherein the cap layer is separated corresponding to the semiconductor chips to form dicing lines for exposing portions of the metal foil.

8. The method of claim 7, wherein the cap layer is made of an insulating material or a metallic material.

9. The method of claim 6, further comprising forming a plurality of solder balls on the portions of the wiring layer exposed from the openings of the insulating protective layer before cutting the encapsulant, the dielectric layer and the insulating protective layer.

10. The method of claim 6, wherein the active surfaces of the semiconductor chips further have a buffer layer formed thereon.

11. The method of claim 6, wherein a plastic film and a second adhesive layer are interposed between the first adhesive layer and the carrier board such that the plastic film is disposed between the first adhesive layer and the second adhesive layer, and the second adhesive layer is disposed between the plastic film and the carrier board, and removing the first adhesive layer further comprises removing the plastic film and the second adhesive layer.

12. The method of claim 6, wherein the semiconductor chips are fabricated by:

providing a semiconductor wafer having an active surface and an opposite inactive surface, and forming a plurality of electrode pads on the active surface of the semiconductor wafer;

forming a plurality of metal bumps on the electrode pads, respectively;

thinning the semiconductor wafer from the inactive surface thereof; and

cutting the semiconductor wafer to obtain the plurality of semiconductor chips.

13. The method of claim 6, wherein the metal foil is fabricated by:

forming on a metal board a resist layer having a plurality of patterned opening areas formed therein for exposing portions of the metal board, respectively;

etching the portions of the metal board exposed from the patterned opening areas of the resist layer such that the metal foil and the metal posts thereon are formed; and

removing the resist layer.