CHIP PACKAGE WITH A CHIP EMBEDDED IN A WIRING BODY

• US 20120273947A1
• Filed: 08/27/2010
• Published: 11/01/2012
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Mo, Zhimin
• Granted Patent: US 8,749,049 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

An electronic device is disclosed. The electronic device comprises at least one electronic chip and a package for the electronic chip. The package comprises a laminate substrate, wherein the electronic chip is attached on the laminate substrate. The laminate substrate comprises one or more conduction layers, one or more insulation layers and a plurality of pads formed in a conduction layer on the side of the laminate substrate opposite to the side connected to the electronic chip. Furthermore, the package comprises an insulation body formed around the electronic chip. Moreover, the package comprises a plurality of electrodes that extend through the insulation body. For each pad of the laminate substrate, wiring is formed in the one or more of conduction layers and in one or more vias passing through the one or more insulation layers for electrically connecting the pad with at least one of the electrodes. The package further comprises an interconnection body formed on the insulation body and the electronic chip. The interconnection body comprises a plurality of pads on the side of the interconnection body opposite to the side connected to the insulation body and the electronic chip and it also comprises wiring inside the interconnection body for electrical connections between the pads of the electronic chip, the electrodes and the pads of the interconnection body. A method for manufacturing the electronic device is also disclosed.

Claims

1. An electronic device comprising:

at least one electronic chip having interconnection pads on a first side of the electronic chip; and

a package for the electronic chip comprising;

a laminate substrate made from a laminate of one or more conduction layers comprising electrically conductive material and one or more insulation layers of dielectric material, wherein the electronic chip is attached on a first side and in a first area of the laminate substrate with a second side of the electronic chip, opposite to the first side of the electronic chip, facing the first side of the laminate substrate, and the laminate substrate comprises a plurality of pads formed in the conduction layer of the laminate substrate on a second side of the laminate substrate, opposite to the first side of the laminate substrate;

a insulation body of electrically insulating material formed on the first side of the laminate substrate around the electronic chip, wherein a first surface of the insulation body is essentially coplanar with the first side of the electronic chip;

a plurality of electrodes of electrically conductive material formed on the first side and in a second area of the laminate substrate, wherein the second area is outside the first area, and the electrodes extend through the insulation body;

for each pad of said plurality of pads of the laminate substrate, wiring formed in one or more of the conduction layers of the laminate substrate and one or more electrically conductive vias passing through one or more of the insulation layers of the laminate substrate for electrically connecting the pad with at least one of the electrodes; and

an interconnection body formed on the first surface of the insulation body and the first side of the electronic chip, wherein the interconnection body comprises a plurality of pads on a side of the interconnection body opposite to the side of the interconnection body that faces the electronic chip and the insulation body, and wiring for electrical connections among the pads of the electronic chip, the electrodes, and the pads of the interconnection body.

2. The electronic device according to claim 1, wherein the interconnection body is formed using a thin-film process for generating said pads of the interconnection body, said wiring of the interconnection body, and electrically insulating material of the interconnection body.

3. The electronic device according to claim 1, wherein at least one of the insulation layers of the laminate substrate comprises a polymer resin material.

4. The electronic device according to claim 3, wherein the polymer resin material is reinforced.

5. The electronic device according to claim 3, wherein the polymer resin material comprises Ajinomoto Build-up Film, benzocyclobutene, bismaleimide-triazine, epoxy, polyester, polyimide, and/or TEFLON.

6. The electronic device according to any prcccding claim claim 1, wherein the laminate substrate is formed using an organic ball-grid array, BGA, substrate manufacturing process.

7. The electronic device according to claim 1, wherein the insulation body is transfer molded.

8. The electronic device according to claim 1, further comprising solder balls attached to one or more pads of the interconnection body and/or one or more pads of the laminate substrate.

9. An electronic apparatus comprising a first electronic device according to claim 1.

10. The electronic apparatus according to claim 9, further comprising a printed circuit board, PCB, and a second electronic device according to claim 1, wherein the first electronic device is mounted on the PCB and the second electronic device is mounted on the first electronic device in a 3D packaging fashion.

11. The electronic apparatus according to claim 9, wherein the electronic apparatus is a portable electronic apparatus, a mobile telephone, a computer, a portable media player, a satellite navigation device, a pager, a communicator, an electronic organizer, a smart phone, or a personal digital assistant, PDA.

12. A method for manufacturing the electronic device according to claim 1, comprising:

attaching the electronic chip to the laminate substrate;

forming the insulation body with molding;

providing holes through the insulation body at the locations where the electrodes are to be formed;

generating the electrodes by supplying the electrically conductive material thereof in said holes provided in the insulation body; and

forming the interconnection body by repeatedly performing thin-film deposition, or plating, and selective removal of alternately dielectric and electrically conductive materials.

13. The method according to claim 12, wherein supplying the electrically conductive material of the electrodes comprises supplying the electrically conductive material with plating or sputtering.

14. The method according to claim 12, further comprising attaching solder balls to one or more pads of the interconnection body and/or one or more pads of the laminate substrate.

15. The method according to claim 12, comprising forming the laminate substrate using an organic BGA substrate manufacturing process.

16. The method according to claim 12, wherein forming the insulation body with molding comprises:

placing the laminate substrate with the electronic chip attached thereto in a transfer mold; and

injecting a molding compound into the transfer mold for forming the insulation body.