SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE DESIGN METHOD, SEMICONDUCTOR DESIGN APPARATUS, AND PROGRAM

• US 20120273973A1
• Filed: 04/20/2012
• Published: 11/01/2012
• Est. Priority Date: 04/28/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TOMODA, Masafumi, Tsukuda, Masayuki
• Granted Patent: US 8,713,508 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06153 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]

Abstract

A potential-supply connection interconnect is provided in a multilayer interconnect layer. The potential supply connection interconnect overlaps some cell of I/O cells in the outer peripheral cell column and some cell of I/O cells in the inner peripheral cell column in a plan view. The potential-supply connection interconnect connects a power potential supply interconnect located below the outer peripheral cell column to a power potential supply interconnect located below the inner peripheral cell column and also connects a ground potential supply interconnect located below the outer peripheral cell column to a ground potential supply interconnect located below the inner peripheral cell column.

Claims

1. A semiconductor device comprising:

a semiconductor chip, the semiconductor chip including;

a substrate;

a multilayer interconnect layer formed over the substrate;

an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell;

an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell;

a potential supply cell provided in at least either the outer peripheral cell column or the inner peripheral cell column, the potential supply cell being either a power potential supply cell or a ground potential supply cell;

electrode pads formed in the uppermost interconnect layer of the multilayer interconnect layer, at least one of the electrode pads being provided in the first I/O cell, at least one of the electrode pads being provided in the potential supply cell, at least one of the electrode pads being provided in the second I/O cell;

a first potential supply interconnect provided in an interconnect layer below the uppermost interconnect layer, the first potential supply interconnect being extending in the same direction as the outer peripheral cell column, the first potential supply interconnect being connected to the first I/O cell;

a second potential supply interconnect provided in another or the interconnect layer below the uppermost interconnect layer, the second potential supply interconnect being extending in the same direction as the inner peripheral cell column, the second potential supply interconnect being located at an inner peripheral side of the first potential supply interconnect in a plan view, the second potential supply interconnect being connected to the second I/O cell; and

a potential-supply connection interconnect connecting the first potential supply interconnect and the second potential supply interconnect,

wherein the potential supply cell directly connects to either one of the first potential supply interconnect or the second potential supply interconnect, and the potential supply cell connects through the one and the potential-supply connection interconnect to the other one of the first potential supply interconnect or the second potential supply interconnect.

2. The semiconductor device according to claim 1,

wherein the potential-supply connection interconnect is formed in another or the interconnect layer below the uppermost interconnect layer.

3. The semiconductor device according to claim 1,

wherein the potential-supply connection interconnect is formed to overlap some cell of the first I/O cells and some cell of the second I/O cells in a plan view.

4. The semiconductor device according to claim 1,

wherein the potential supply cell is provided in the outer peripheral cell column but not provided in the inner peripheral cell column.

5. The semiconductor device according to claim 1,

wherein either the outer peripheral cell column or the inner peripheral cell column that has the potential supply cell has:

both a power potential supply cell and a ground potential supply cell serving as the potential supply cell;

a first power supply interconnect and a first ground interconnect serving as the first potential supply interconnect;

a second power supply interconnect and a second ground interconnect serving as the second potential supply interconnect; and

a power connection interconnect and a ground connection interconnect serving as the potential-supply connection interconnect, the power connection interconnect being connecting the first power supply interconnect to the second power supply interconnect, the ground connection interconnect being connecting the first ground interconnect to the second ground interconnect,

either the first supply interconnect or the second power supply interconnect is connected to the power potential supply cell, and

either the first ground interconnect or the second ground interconnect is connected to the ground potential supply cell.

6. The semiconductor device according to claim 1,

wherein the first I/O cell included in the outer peripheral cell column and the second I/O cell included in the inner peripheral cell column inward next to the outer peripheral cell column are disposed at the same position relative to a direction along the edge of the substrate.

7. The semiconductor device according to claim 6,

wherein the potential-supply connection interconnect extends from below one of the electrode pads of the plurality of first I/O cells toward below one of the electrode pads of the second I/O cells, and extends from below another of the electrode pads of the plurality of first I/O cells toward below another of the electrode pads of the second I/O cells, and

the potential-supply connection interconnect in each of the plurality of first I/O cells and the plurality of second I/O cells extends in a direction perpendicular to the edge of the substrate, and is repeated with the same shape in left and right halves of the first I/O cells and the second I/O cells in relation to each center of the first I/O cells and the second I/O cells.

8. The semiconductor device according to claim 1,

wherein the first I/O cell included in the outer peripheral cell column and the second I/O cell included in the inner peripheral cell column inward next to the outer peripheral cell column are disposed alternately in a direction along the edge of the substrate.

9. The semiconductor device according to claim 8,

wherein a plurality of first potential-supply connection interconnects in the outer peripheral cell column extend in a direction perpendicular to the edge of the substrate,

a plurality of second potential-supply connection interconnects in the inner peripheral cell column extend in a direction perpendicular to the edge of the substrate, and

one of the plurality of first potential-supply connection interconnects is connected to one of the plurality of second potential-supply connection interconnects, and another of the plurality of first potential-supply connection interconnects is connected to another of the plurality of second potential-supply connection interconnects.

10. The semiconductor device according to claim 1, further comprising:

an interconnect substrate mounting the semiconductor chip; and

a bonding wire connecting the semiconductor chip and the interconnect substrate.

11. The semiconductor device according to claim 1, further comprising:

an interconnect substrate connected to the semiconductor chip through flip-chip bonding.

12. A semiconductor device design method for designing a semiconductor device using a computer, comprising:

disposing an outer peripheral cell column including at least one first I/O cell along an edge of a substrate of the semiconductor device;

disposing at least one inner peripheral cell column including at least one second I/O cell at an inner peripheral side of the outer peripheral cell column;

disposing a potential supply cell in either the outer peripheral cell column or the inner peripheral cell column, the potential supply cell being either a power potential supply cell or a ground potential supply cell;

disposing a first potential supply interconnect in an interconnect layer below the uppermost interconnect layer, the first potential supply interconnect being extending in the same direction as the outer peripheral cell column, the first potential supply interconnect being connected to the first I/O cell;

disposing a second potential supply interconnect in another or the interconnect layer below the uppermost interconnect layer, the second potential supply interconnect being extending in the same direction as the inner peripheral cell column, the second potential supply interconnect being located at an inner peripheral side of the first potential supply interconnect in a plan view, the second potential supply interconnect being connected to the second I/O cell;

connecting the potential supply cell to either the first potential supply interconnect or the second potential supply interconnect that overlaps the potential supply cell; and

disposing a potential-supply connection interconnect connecting the first potential supply interconnect to the second potential supply interconnect.

13. A semiconductor device design apparatus supporting design of a semiconductor device, comprising:

a cell arrangement unit;

disposing an outer peripheral cell column including at least one first I/O cell along an edge of a substrate of the semiconductor device;

disposing at least one inner peripheral cell column including at least one second I/O cell at an inner peripheral side of the outer peripheral cell column; and

disposing a potential supply cell in either the outer peripheral cell column or the inner peripheral cell column, the potential supply cell being either a power potential supply cell or a ground potential supply cell,

a potential supply interconnect arrangement unit;

disposing a first potential supply interconnect in an interconnect layer below the uppermost interconnect layer, the first potential supply interconnect being extending in the same direction as the outer peripheral cell column, the first potential supply interconnect being connected to the first I/O cell;

disposing a second potential supply interconnect in another or the interconnect layer below the uppermost interconnect layer, the second potential supply interconnect being extending in the same direction as the inner peripheral cell column, the second potential supply interconnect being located at an inner peripheral side of the first potential supply interconnect in a plan view, the second potential supply interconnect being connected to the second I/O cell; and

connecting the potential supply cell to either the first potential supply interconnect or the second potential supply interconnect that overlaps the potential supply cell, and

a connection interconnect arrangement unit disposing a potential-supply connection interconnect connecting the first potential supply interconnect to the second potential supply interconnect.

14. A program causing a computer to function as a semiconductor device design apparatus supporting design of a semiconductor device, the program causing the computer to have:

a function of;

disposing an outer peripheral cell column including at least one first I/O cell along an edge of a substrate of the semiconductor device;

disposing at least one inner peripheral cell column including at least one second I/O cell at an inner peripheral side of the outer peripheral cell column; and

disposing a potential supply cell in either the outer peripheral cell column or the inner peripheral cell column, the potential supply cell being either a power potential supply cell or a ground potential supply cell,

a function of;

disposing a first potential supply interconnect in an interconnect layer below the uppermost interconnect layer, the first potential supply interconnect being extending in the same direction as the outer peripheral cell column, the first potential supply interconnect being connected to the first I/O cell;

disposing a second potential supply interconnect in another or the interconnect layer below the uppermost interconnect layer, the second potential supply interconnect being extending in the same direction as the inner peripheral cell column, the second potential supply interconnect being located at an inner peripheral side of the first potential supply interconnect in a plan view, the second potential supply interconnect being connected to the second I/O cell; and

connecting the potential supply cell to either the first potential supply interconnect or the second potential supply interconnect that overlaps the potential supply cell, and

a function of disposing a potential-supply connection interconnect connecting the first potential supply interconnect to the second potential supply interconnect.