Method and Apparatus for Power Domain Isolation during Power Down

• US 20120275236A1
• Filed: 04/27/2011
• Published: 11/01/2012
• Est. Priority Date: 04/27/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hess, Greg M., Javarappa, Naveen
• Granted Patent: US 8,570,788 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. The circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain.

Claims

1. An integrated circuit comprising:

a first functional unit in a first power domain;

a second functional unit in a second power domain;

a gating circuit coupled between the first functional unit and the second functional unit, wherein the first functional unit is coupled to the second functional unit via the gating circuit, and wherein the gating circuit is configured to be, when enabled, transparent to a signal conveyed between the first functional unit and the second functional unit;

an isolation circuit, wherein the isolation circuit is configured to disable the gating circuit prior to powering down one of the first or second functional units, wherein the gating circuit is configured to, when disabled, inhibit signals from being conveyed between the first and second functional units.

2. The integrated circuit as recited in claim 1, wherein the second functional unit includes one or more dynamic logic circuits, and wherein the first functional unit includes one or more corresponding dynamic-to-static converter circuits.

3. The integrated circuit as recited in claim 2, wherein the first functional unit includes an input circuit coupled to receive an input signal from the second functional units, wherein the input circuit is configured to, when active, drive a first bit line.

4. The integrated circuit as recited in claim 3, wherein the bit line is coupled to the gating circuit, wherein the gating circuit is coupled between the first bit line and the second bit line, and wherein the isolation circuit is configured to disable the gating circuit prior to powering down the second functional unit.

5. The integrated circuit as recited in claim 1, wherein the second functional unit is a memory circuit.

6. An apparatus comprising:

a memory comprising a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a respective bit line;

a redundancy multiplexer coupled to receive a first bit line of the respective bit lines and a second bit line of the respective bit lines, wherein the redundancy multiplexer includes a first passgate device coupled to the first bit line and a second passgate device coupled to the second bit line; and

a control circuit coupled to the redundancy multiplexer and configured to generate a first control signal to the first passgate device and a second control signal to the second passgate device, wherein the control circuit is configured to disable each of the first passgate device and the second passgate device responsive to assertion of an isolation signal.

7. The apparatus as recited in claim 6, wherein the redundancy multiplexer and the control circuit are in a first power domain and wherein the memory is in a second power domain, and wherein the control circuit is configured to assert the isolation signal prior to removing power from the memory.

8. The apparatus as recited in claim 6, wherein the first passgate device is coupled between the first bit line and a third bit line, and wherein the second passgate device is coupled between the second bit line and the third bit line;

wherein the apparatus includes a first precharge circuit coupled to the third bit line, wherein the first precharge circuit is configured to, when active, precharge the third bit line; and

wherein the apparatus includes a second precharge circuit, wherein the second precharge circuit is configured to, when enabled and active, precharge the first bit line.

9. The apparatus as recited in claim 6, wherein the apparatus includes an isolation unit configured to assert the isolate signal, wherein the isolation unit is configured to assert the isolate signal prior to a power management unit powering up a functional unit in the first power domain.

10. The apparatus as recited in claim 9, wherein the isolation unit is configured to assert the isolate signal prior to the power management unit powering down the functional unit in the first power domain.

11. A method comprising:

a power management unit asserting a control signal responsive to determining to power down a first functional unit in a first power domain that is coupled to provide signals to a second functional unit in a second power domain;

disabling one or more gating circuits coupled between the first functional unit and the second functional unit;

inhibiting signals from being provided from the first functional unit to the second functional unit responsive disabling the one or more gating circuits;

removing power from the first functional unit subsequent to disabling the one or more gating circuits.

12. The method as recited in claim 11, wherein disabling the one or more gating circuits includes disabling at least one of a passgate coupled between a first bit line and a second bit line and a redundant passgate coupled between a third bit line and the second bit line.

13. The method as recited in claim 12, further comprising providing the control signal to a redundancy decoder.

14. The method as recited in claim 13, further comprising the redundancy decoder asserting a redundancy control signal responsive to receiving the control signal.

15. The method as recited in claim 11, further comprising removing power from circuitry in the second power domain subsequent to removing power from the circuitry in the first power domain.

18. The integrated circuit as recited in claim 15, wherein each of the plurality of pull-down circuits is an n-channel metal oxide semiconductor (NMOS) transistor configured to pull its corresponding one of the plurality of bit lines low responsive to receiving a high on its respective gate terminal.

19. The integrated circuit as recited in claim 18, wherein each of the plurality of bit lines includes a first segment coupled between a corresponding one of the plurality of pull-down circuits and a corresponding one of the first plurality of passgates, and a second segment coupled to each of the first plurality of passgates and a corresponding one of a plurality of dynamic-to-static converter circuits, wherein each of the dynamic-to-static converter circuits includes a precharge circuit coupled to the second segment of the corresponding one of the plurality of bit lines.

20. The integrated circuit as recited in claim 19, further comprising a second plurality of passgates forming a redundancy multiplexer, wherein each of the second plurality of passgates is coupled between the first segment of one of the plurality of bit lines and the second segment of another one of the plurality of bit lines.

16. An integrated circuit comprising:

a static random access memory (SRAM) in a first power domain;

a processor core in a second power domain, wherein the processor core is coupled to receive a plurality of signals via corresponding ones of a plurality of bit lines;

a plurality of pull-down circuits, wherein each of the plurality of pull-down circuits is coupled between the SRAM and a corresponding one of the plurality of bit lines, wherein each of the plurality of pull-down circuits is configured to generate corresponding ones of the plurality of signals based on data received from the SRAM during a read operation;

a first plurality of passgates each configured to, when activated, allow corresponding signals to be conveyed from the SRAM via corresponding ones of the plurality of bit lines;

a control circuit coupled to each of the plurality of passgates, wherein the control circuit is configured to deactivate any active ones of the plurality of passgates responsive to receiving an indication that circuitry of both the first and second domains is to be powered down.

17. The integrated circuit as recited in claim 16, further comprising a power management unit, wherein the power management circuit is configured to:

provide the indication to the control circuit;

remove power from circuitry of the second power domain subsequent to the control circuit deactivating the active ones of the plurality of passgate circuits; and

remove power from the circuitry of the first power domain subsequent to removing power from the circuitry of the second power domain.

21. A system comprising:

a memory in a first power domain;

a plurality of pull-down circuits each coupled to receive a corresponding one of a plurality of signals from the memory during a read operation, wherein each of the pull-down circuits is coupled to a corresponding one of a plurality of global bit lines;

a first plurality of passgate circuits each coupled to a corresponding one of the plurality of global bit lines;

a plurality of dynamic-to-static converter circuits in a second power domain, wherein each of the plurality of dynamic-to-static converter circuits is coupled to a corresponding one of the plurality of global bit lines, wherein each of the first plurality of passgate circuits is configured to, when active, enable signals to be conveyed across a corresponding one of the plurality of global bit lines from a corresponding one of the plurality of pull-down circuits to a corresponding one of the plurality of dynamic-to-static converter circuits; and

a control circuit configured to deactivate each of the first plurality of passgate circuits responsive to receiving an indication that the memory is to be powered down.

22. The system as recited in claim 21, further comprising a power management unit configured to provide the indication to the control circuit, wherein the power management unit is further configured to remove power from the memory subsequent to the control circuit deactivating each of the first plurality of passgate circuits.

23. The system as recited in claim 21, further comprising a second plurality of passgate circuits, wherein the second plurality of passgate circuits forms a redundancy multiplexer, and wherein each of the second plurality of passgate circuits is coupled between a corresponding pair of the plurality of global bit lines.