SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CIRCUIT

• US 20120275244A1
• Filed: 12/07/2011
• Published: 11/01/2012
• Est. Priority Date: 04/28/2011
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: DO, Chang-Ho
• Application Number:
  US13/313,370
• Publication Number:
  US 20120275244A1
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

A semiconductor integrated circuit includes: a fuse; a first driving unit configured to drive a sensing node in response to a first fuse sensing signal; a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.

Claims

1. A semiconductor integrated circuit comprising:

a fuse;

a first driving unit configured to drive a sensing node in response to a first fuse sensing signal;

a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the fuse form a driving path;

a bypass resistor unit connected in parallel with the fuse; and

a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.

2. The semiconductor integrated circuit of claim 1, wherein the first fuse sensing signal activates the first driving unit in a turn on state in a sensing node initialization period and deactivates the first driving node in a turn off state in a subsequent period.

3. The semiconductor integrated circuit of claim 2, wherein the second fuse sensing signal activates the second driving unit to a turn on state in a fuse state sensing period and deactivates the second driving unit to a turn off state in a subsequent period.

4. The semiconductor integrated circuit of claim 3, wherein the first driving unit is provided between a pull-down voltage source and the sensing node, and the second driving unit is provided between a pull-up voltage source and the sensing node.

5. The semiconductor integrated circuit of claim 3, wherein the first driving unit is provided between a pull-up voltage source and the sensing node, and the second driving unit is provided between a pull-down voltage source and the sensing node.

6. The semiconductor integrated circuit of claim 1, wherein the sensing unit includes an inverter having an input terminal that is connected to the sensing node.

7. A semiconductor integrated circuit comprising:

a fuse;

an NMOS transistor configured to pull-down drive a sensing node in response to a first fuse sensing signal;

a PMOS transistor configured to pull-up drive the sensing node in response to a second fuse sensing signal, wherein the PMOS transistor and the fuse form a driving path;

a bypass resistor unit connected in parallel with the fuse; and

a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.

8. The semiconductor integrated circuit of claim 7,

wherein the fuse has a first end that is connected to the sensing node, and

wherein the PMOS transistor has a source that is connected to a pull-up voltage source, a drain that is connected to a second end of the fuse, and a gate that receives the second fuse sensing signal.

9. The semiconductor integrated circuit of claim 7,

wherein the fuse has a first end that is connected to a pull-up voltage source, and

wherein the PMOS transistor has a source that is connected to a second end of the fuse, a drain that is connected to the sensing node, and a gate that receives the second fuse sensing signal.

10. The semiconductor integrated circuit of claim 8, wherein the first fuse sensing signal is activated to a logic high level in a sensing node initialization period and transitions to a logic low level in a subsequent period.

11. The semiconductor integrated circuit of claim 10, wherein the second fuse sensing signal is activated to a logic low level in a fuse state sensing period and transitions to a logic high level in a subsequent period.

12. The semiconductor integrated circuit of claim 7, wherein the sensing unit comprises:

a first inverter having an input terminal that is connected to the sensing node; and

a second inverter configured to receive an output signal of the first inverter as an input thereof and have an output terminal that is connected to the sensing node.

13. The semiconductor integrated circuit of claim 12, wherein, when the fuse is not cut, a ratio between an effective resistance of the PMOS transistor, the bypass resistor unit, and the fuse and an effective resistance of a pull-down NMOS transistor included in the second inverter generates a voltage of the sensing node that is less than a logic low input characteristic value of the first inverter.

14. The semiconductor integrated circuit of claim 12, wherein, when the fuse is cut, a ratio between an effective resistance of the PMOS transistor and the bypass resistor unit and an effective resistance of a pull-down NMOS transistor included in the second inverter generates a voltage of the sensing node that is greater than a logic high input characteristic value of the first inverter.

15. A semiconductor integrated circuit comprising:

a fuse;

an NMOS transistor configured to pull-down drive a sensing node in response to a first fuse sensing signal;

a first PMOS transistor configured to pull-up drive the sensing node in response to a second fuse sensing signal;

a second PMOS transistor configured to pull-up drive the sensing node in response to the first fuse sensing signal, wherein the first and second PMOS transistor and the fuse form a driving path;

a bypass resistor unit connected in parallel with the fuse; and

a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.

16. The semiconductor integrated circuit of claim 15,

wherein the first PMOS transistor has a source that is connected to a pull-up voltage source, a drain that is connected to a first end of the fuse, and a gate that receives the second fuse sensing signal, and

wherein the second PMOS transistor has a source that is connected to a second end of the fuse, a drain that is connected to the sensing node, and a gate that receives the first fuse sensing signal.

17. The semiconductor integrated circuit of claim 15,

wherein the second PMOS transistor has a source that is connected to a pull-up voltage source, a drain that is connected to a first end of the fuse, and a gate that receives the first fuse sensing signal, and

wherein the first PMOS transistor has a source that is connected to a second end of the fuse, a drain that is connected to the sensing node, and a gate that receives the second fuse sensing signal.

18. The semiconductor integrated circuit of claim 16, wherein the first fuse sensing signal is activated to a logic high level in a sensing node initialization period and transitions to a logic low level in a subsequent period.

19. The semiconductor integrated circuit of claim 18, wherein the second fuse sensing signal is activated to a logic low level in a fuse state sensing period and transitions to a logic high level in a subsequent period.

20. The semiconductor integrated circuit of claim 15, wherein the sensing unit comprises:

a first inverter having an input terminal that is connected to the sensing node; and

a second inverter configured to receive an output signal of the first inverter as an input thereof and have an output terminal that is connected to the sensing node.

21. The semiconductor integrated circuit of claim 20, wherein, when the fuse is not cut, a ratio between an effective resistance of the first and second PMOS transistors, the bypass resistor unit and the fuse and an effective resistance of a pull-down NMOS transistor included in the second inverter generates a voltage of the sensing node that is less than a logic low input characteristic value of the first inverter.

22. The semiconductor integrated circuit of claim 20, wherein, when the fuse is cut, a ratio between an effective resistance of the first and second PMOS transistors and the bypass resistor unit and an effective resistance of a pull-down NMOS transistor included in the second inverter generates a voltage of the sensing node that is greater than a logic high input characteristic value of the first inverter.

23. A semiconductor integrated circuit comprising:

a fuse;

a PMOS transistor configured to pull-up drive a sensing node in response to a first fuse sensing signal;

an NMOS transistor configured to pull-down drive the sensing node in response to a second fuse sensing signal, wherein the NMOS transistor and the fuse form a driving path;

a bypass resistor unit connected in parallel with the fuse; and

a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.

24. The semiconductor integrated circuit of claim 23,

wherein the fuse has a first end that is connected to the sensing node, and

wherein the NMOS transistor has a source that is connected to a pull-down voltage source, a drain that is connected to a second end of the fuse, and a gate that receives the second fuse sensing signal.

25. The semiconductor integrated circuit of claim 23,

wherein the fuse has a first end that is connected to a pull-up voltage source, and

wherein the NMOS transistor has a source that is connected to a second end of the fuse, a drain that is connected to the sensing node, and a gate that receives the second fuse sensing signal.

26. The semiconductor integrated circuit of claim 24, wherein the first fuse sensing signal is activated to a logic low level in a sensing node initialization period and transitions to a logic high level in a subsequent period.

27. The semiconductor integrated circuit of claim 26, wherein the second fuse sensing signal is activated to a logic high level in a fuse state sensing period and transitions to a logic low level in a subsequent period.

28. The semiconductor integrated circuit of claim 23, wherein the sensing unit comprises:

a first inverter having an input terminal that is connected to the sensing node; and

a second inverter configured to receive an output signal of the first inverter as an input thereof and have an output terminal that is connected to the sensing node.

29. The semiconductor integrated circuit of claim 28, wherein, when the fuse is not cut, a ratio between an effective resistance of the NMOS transistor, the bypass resistor unit and the fuse and an effective resistance of a pull-up PMOS transistor included in the second inverter generates a voltage of the sensing node that is less than a logic low input characteristic value of the first inverter.

30. The semiconductor integrated circuit of claim 28, wherein, when the fuse is cut, a ratio between an effective resistance of the NMOS transistor and the bypass resistor unit and an effective resistance of a pull-up PMOS transistor included in the second inverter generates a voltage of the sensing node that is greater than a logic high input characteristic value of the first inverter.

31. A semiconductor integrated circuit comprising:

a fuse;

a PMOS transistor configured to pull-up drive a sensing node in response to a first fuse sensing signal;

a first NMOS transistor configured to pull-down drive the sensing node in response to a second fuse sensing signal;

a second NMOS transistor the first NMOS transistor and configured to pull-down drive the sensing node in response to the first fuse sensing signal, wherein the first and second NMOS transistor and the fuse form a driving path;

a bypass resistor unit connected between both ends of the fuse; and

a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.

32. The semiconductor integrated circuit of claim 31,

wherein the first NMOS transistor has a source that is connected to a pull-down voltage source, a drain that is connected to a first end of the fuse, and a gate that receives the second fuse sensing signal, and

wherein the second NMOS transistor has a source that is connected to a second end of the fuse, a drain that is connected to the sensing node, and a gate that receives the first fuse sensing signal.

33. The semiconductor integrated circuit of claim 31,

wherein the second NMOS transistor has a source that is connected to a pull-down voltage source, a drain that is connected to a first end of the fuse, and a gate that receives the first fuse sensing signal, and

wherein the first NMOS transistor has a source that is connected to a second end of the fuse, a drain that is connected to the sensing node, and a gate that receives the second fuse sensing signal.

34. The semiconductor integrated circuit of claim 32, wherein the first fuse sensing signal is activated to a logic low level in a sensing node initialization period and transitions to a logic high level in a subsequent period.

35. The semiconductor integrated circuit of claim 34, wherein the second fuse sensing signal is activated to a logic high level in a fuse state sensing period and transitions to a logic low level in a subsequent period.

36. The semiconductor integrated circuit of claim 31, wherein the sensing unit comprises:

a first inverter having an input terminal that is connected to the sensing node; and

a second inverter configured to receive an output signal of the first inverter as an input thereof and have an output terminal that is connected to the sensing node.

37. The semiconductor integrated circuit of claim 36, wherein, when the fuse is not cut, a ratio between an effective resistance of the first and second NMOS transistors, the bypass resistor unit and the fuse and an effective resistance of a pull-up PMOS transistor included in the second inverter generates a voltage of the sensing node that is less than a logic low input characteristic value of the first inverter.

38. The semiconductor integrated circuit of claim 36, wherein, when the fuse is cut, a ratio between an effective resistance of the first and second NMOS transistors and the bypass resistor unit and an effective resistance of a pull-up PMOS transistor included in the second inverter generates a voltage of the sensing node that is greater than a logic high input characteristic value of the first inverter.

39. A semiconductor memory device comprising:

a plurality of fuses;

a first driving unit configured to pull-up drive a common sensing node in response to a precharge signal;

a plurality of second driving units configured to pull-down drive the common sensing node in response to corresponding address information, wherein the plurality of second driving units and corresponding fuses form driving paths;

a plurality of bypass resistor units connected in parallel with corresponding fuses; and

a sensing unit configured to sense a programming state of each of the plurality of fuses in response to a voltage of the common sensing node.

40. The semiconductor integrated circuit of claim 39, wherein the precharge signal is activated by receiving a precharge command and is deactivated by receiving an active command.

41. The semiconductor integrated circuit of claim 40, wherein the respective address informations are sequentially activated by receiving the active command, and an activation period is shorter than tRCDmin (a minimum value of a Ras to Cas delay time).