Superjunction Structures for Power Devices and Methods of Manufacture

• US 20120276701A1
• Filed: 04/27/2011
• Published: 11/01/2012
• Est. Priority Date: 04/27/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Rinehimer, Mark L., Shenoy, Praveen Muraleedharan
• Granted Patent: US 8,673,700 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Claims

1-150. -150. (canceled)

151. A method for forming pillars of alternating conductivity type in a power device, the method comprising:

forming one or more N-type epitaxial layers over a substrate;

forming P-type body regions in the one or more N-type epitaxial layers;

forming gate electrodes extending adjacent to but being insulated from the one or more N-type epitaxial layers by a gate dielectric;

after forming the P-type body regions and the gate electrodes, forming a plurality of deep trenches extending in the one or more N-type epitaxial layers; and

filling the plurality of deep trenches with P-type silicon to form a plurality of P−

pillars, those portions of the one or more N-type epitaxial layers separating the plurality of P−

pillars forming N-pillars such that the P-pillars and the N-pillars form pillars of alternating conductivity type.

152. The method of claim 151 wherein a composite layer of oxide-nitride-oxide (ONO) is used in defining and etching the plurality of deep trenches in the N-type epitaxial layer.

153. The method of claim 151 further comprising:

forming N-type source regions in the P-type body regions, wherein the plurality of deep trenches are formed after forming the source regions.

154. The method of claim 153 further comprising:

after forming the plurality of deep trenches, forming a dielectric cap over each gate electrode, the dielectric caps defining contact openings between adjacent trenches.

155. The method of claim 154 further comprising:

implanting P-type dopants into the P-type body regions through the contact openings to form P+ heavy body regions in the P-type body regions.

156. The method of claim 155 further comprising:

prior to forming the dielectric cap, forming a conformal layer that extends adjacent the gate electrodes such that the conformal layer spaces the P-type dopants implanted into the P-type body regions from the edges of the gate electrodes.

157. The method of claim 154 comprising:

etching a dimple in each P-type body region; and

implanting P-type dopants into the bottom of each dimple to form heavy body regions in the P-type body regions.

158. The method of claim 154 further comprising:

forming a source metal layer electrically contacting the N-type source regions and the P+ heavy body regions through the contact openings.

159. The method of claim 151 wherein the power device includes an active region and a termination regions surrounding the active region, both the active and termination regions include a plurality of P-pillars, the method further comprising:

prior to forming the P-type body regions, forming a P-type Iso region in the one or more N-type epitaxial layers in the termination region such that after the plurality of P-pillars are formed, the P-type Iso region connects a predetermined number of the P-pillars in the termination region together.

160. The method of claim 159 further comprising:

forming a source metal layer electrically contacting the P-type Iso region.

161. The method of claim 151 wherein the step of forming gate electrodes further comprises:

forming shallow trenches extending into the one or more N-type epitaxial layers;

forming a gate dielectric layer lining the sidewalls of the shallow trenches; and

forming recessed gate electrodes in the shallow trenches.

162. The method of claim 151 wherein the step of forming gate electrodes further comprises:

forming a gate dielectric layer over the one or more N-type epitaxial layers; and

forming planar gate electrodes over the gate dielectric layer, the planar gate electrodes being laterally spaced from one another, and the plurality of deep trenches are formed between the planar gate electrodes.

163-171. -171. (canceled)