SELECTIVE ERROR DETECTION AND ERROR CORRECTION FOR A MEMORY INTERFACE
First Claim
1. In a data processing device comprising a processor unit coupled to a memory, a method comprising:
- receiving a write access comprising data to be written to the memory;
executing a first error detection procedure in response to receiving the write access, the first error detection procedure comprising;
in response to determining the data is of a first size, performing error detection on the data;
in response to determining the data is of a second size, writing the data to memory without performing error detection on the data.
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Abstract
Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.
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Citations
20 Claims
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1. In a data processing device comprising a processor unit coupled to a memory, a method comprising:
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receiving a write access comprising data to be written to the memory; executing a first error detection procedure in response to receiving the write access, the first error detection procedure comprising; in response to determining the data is of a first size, performing error detection on the data; in response to determining the data is of a second size, writing the data to memory without performing error detection on the data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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receiving a write access comprising data to be written to the memory; determining an access control policy in response to the write access; selectively performing a first error detection procedure for the write access at the memory based on the access control policy; - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A data processing device, comprising:
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a source module to generate, for a write access, a set of ECC checkbits based on data to be written; a memory; an interconnect to provide the write access to the memory; a storage location to store access control policy information; and the memory comprising an ECC module to selectively perform a first error detection procedure on the data based on the access control policy. - View Dependent Claims (18, 19, 20)
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Specification