SEMICONDUCTOR DEVICE, MEMORY DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

• US 20120280225A1
• Filed: 04/25/2012
• Published: 11/08/2012
• Est. Priority Date: 05/06/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SAKATA, Junichiro
• Granted Patent: US 8,809,928 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An oxide semiconductor is used for a semiconductor layer of a transistor included in a semiconductor device, whereby leakage current between a source and a drain can be reduced, so that reduction in power consumption of a semiconductor device and a memory device including the semiconductor device and an improvement in characteristics of retaining stored data (electric charge) in the semiconductor device and the memory device can be achieved. Further, a drain electrode of the transistor, the semiconductor layer, and a first electrode which overlaps with the drain electrode form a capacitor, and a gate electrode is led to an overlying layer at a position which overlaps with the capacitor. Thus, the semiconductor device and the memory device including the semiconductor device can be miniaturized.

Claims

1. A semiconductor device comprising:

a source electrode and a drain electrode over an insulating surface;

an oxide semiconductor layer over the source electrode and the drain electrode;

a first electrode over one of the source electrode and the drain electrode with the oxide semiconductor layer interposed therebetween;

a gate insulating layer over and in contact with the oxide semiconductor layer and the first electrode; and

a gate electrode over the gate insulating layer so as to overlap with the first electrode.

2. The semiconductor device according to claim 1, wherein the first electrode is set to a constant potential or a ground potential.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains one or more elements selected from In, Ga, Sn, and Zn.

4. A memory device including the semiconductor device according to claim 1.

5. The semiconductor device according to claim 1, further comprising an interlayer insulating layer over the gate electrode and the gate insulating layer, wherein a contact hole is formed in the interlayer insulating layer so as to overlap with the first electrode.

6. The semiconductor device according to claim 5, wherein the first electrode is set to a constant potential or a ground potential.

7. The semiconductor device according to claim 5, wherein the oxide semiconductor layer contains one or more elements selected from In, Ga, Sn, and Zn.

8. A memory device including the semiconductor device according to claim 5.

9. The semiconductor device according to claim 1, further comprising an interlayer insulating layer over the gate electrode and the gate insulating layer,

wherein at least part of the gate electrode is exposed on a surface of the interlayer insulating layer, and

wherein the part of the gate electrode overlaps with the first electrode.

10. The semiconductor device according to claim 9, wherein the first electrode is set to a constant potential or a ground potential.

11. The semiconductor device according to claim 9, wherein the oxide semiconductor layer contains one or more elements selected from In, Ga, Sn, and Zn.

12. A memory device including the semiconductor device according to claim 9.

13. A method for manufacturing a semiconductor device comprising the steps of:

forming a source electrode and a drain electrode over an insulating surface;

forming an oxide semiconductor layer over the source electrode and the drain electrode;

forming a first electrode over one of the source electrode and the drain electrode with the oxide semiconductor layer interposed therebetween;

forming a gate insulating layer over and in contact with the oxide semiconductor layer and the first electrode;

forming a gate electrode over the gate insulating layer so as to overlap with the first electrode;

forming an interlayer insulating layer over the gate insulating layer and the gate electrode; and

forming a contact hole in the interlayer insulating layer so as to overlap with the first electrode.

14. A method for manufacturing a semiconductor device comprising the steps of:

forming a source electrode and a drain electrode over an insulating surface;

forming an oxide semiconductor layer over the source electrode and the drain electrode;

forming a first electrode over one of the source electrode and the drain electrode with the oxide semiconductor layer interposed therebetween;

forming a gate insulating layer over and in contact with the oxide semiconductor layer and the first electrode;

forming a gate electrode over the gate insulating layer so as to overlap with the first electrode; and

forming an interlayer insulating layer over the gate insulating layer and the gate electrode,

performing a planarization treatment on a surface of the interlayer insulating layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the planarization treatment is performed by a chemical mechanical polishing.

16. The method for manufacturing a semiconductor device according to claim 14,

wherein the planarization treatment is performed so that at least part of the gate electrode is exposed on the surface of the interlayer insulating layer, and

wherein the part of the gate electrode overlaps with the first electrode.

17. A semiconductor device comprising:

a gate electrode over an insulating surface;

a gate insulating layer adjacent to the gate electrode;

an oxide semiconductor layer adjacent to the gate electrode with the gate insulating layer interposed therebetween;

a source electrode and a drain electrode in contact with the oxide semiconductor layer;

a first electrode provided between the gate insulating layer and the oxide semiconductor layer so as to overlap with one of the source electrode and the drain electrode.

18. The semiconductor device according to claim 17, wherein the first electrode is set to a constant potential or a ground potential.

19. The semiconductor device according to claim 17, wherein the oxide semiconductor layer contains one or more elements selected from In, Ga, Sn, and Zn.

20. A memory device including the semiconductor device according to claim 17.