OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20120280227A1
• Filed: 11/22/2010
• Published: 11/08/2012
• Est. Priority Date: 11/27/2009
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Wakana, Hironori, Kawamura, Tetsufumi, Uchiyama, Hiroyuki, Fujii, Kuniharu
• Application Number:
  US13/512,062
• Publication Number:
  US 20120280227A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Features are forming a gate electrode on an insulating substrate; forming a first semiconducting layer mainly composed of an indium oxide and having a film thickness of 5 nm or more onto the gate electrode interposing a gate insulating film; forming a second semiconducting layer mainly composed of zinc and tin oxides without containing indium and having a film thickness of 5 to 50 nm on the first semiconducting layer, and including a step of forming a source electrode and a drain electrode on the second semiconducting layer. In this manner, by combining the materials of the first semiconducting layer and the second semiconducting layer with each other, a semiconductor device with a reduced dependency on the film thickness of the semiconducting layer, little characteristic variations on a large area substrate is provided.

Claims

1. A field-effect transistor comprising:

a gate electrode;

a first semiconducting layer provided on the gate electrode interposing a gate insulating film;

a second semiconducting layer connected to the first semiconducting layer;

a source electrode connected to the second semiconducting layer; and

a drain electrode connected to the second semiconducting layer,

wherein the first semiconducting layer contains In (indium) element and O (oxide) element, and

the second semiconducting layer contains Zn (zinc) element and O element and does not contain In element.

2. The field-effect transistor according to claim 1,

wherein the first semiconducting layer further contains Zn element, Sn (tin) element, Ge (germanium) element or Si (silicon) element.

3. The field-effect transistor according to claim 1,

wherein the second semiconducting layer further contains Sn (tin) element.

4. The field-effect transistor according to claim 1,

wherein the first semiconducting layer and the source electrode are not directly connected to each other.

5. The field-effect transistor according to claim 1,

wherein the source electrode is directly connected to the first semiconducting layer and the second semiconducting layer, and,

when taking a resistance value of a portion through the first semiconducting layer in a resistance between a channel layer of the first semiconducting layer and the source electrode as R1, and taking a resistance value of a portion through the second semiconducting layer in a resistance between the channel layer and the source electrode as R2, R1 is greater than R2.

6. The field-effect transistor according to claim 1,

wherein the first semiconducting layer is designed such that in constituent elements other than oxygen relative to the entire elements, the compounding ratio of In element is 50% or more.

7. The field-effect transistor according to claim 1,

wherein the gate electrode is provided on a substrate of the field-effect transistor,

the gate insulating film is provided on the gate insulating film,

the first semiconducting layer is provided on the gate insulating film,

the second semiconducting layer is provided on the first semiconducting layer, and

the source electrode and the drain electrode are provided on the second semiconducting layer.

8. A method of manufacturing a field-effect transistor comprising:

a first step of forming a first semiconducting layer containing In (indium) element and O (oxide) element on a gate insulating film; and

a second step of forming a second semiconducting layer containing Zn (zinc) element and O element and not containing In element on the first semiconducting film.

9. The method of manufacturing a field-effect transistor according to claim 8,

wherein, after carrying out the first step, a third step of removing the first semiconducting layer except for a predetermined portion is further carried out, and the second step is carried out thereafter.

10. The method of manufacturing a field-effect transistor according to claim 9,

wherein, after carrying out the second step, a fourth step of removing the second semiconducting layer except for a predetermined portion is further carried out.

11. The method of manufacturing a field-effect transistor according to claim 10,

wherein, after carrying out the fourth step, a fifth step of forming a source electrode to be connected to the second semiconducting layer and a drain electrode to be connected to the second semiconducting layer is further carried out.

12. The method of manufacturing a field-effect transistor according to claim 8,

wherein, after carrying out the first step, the second step is carried out, and,

after carrying out the second step, a sixth step of removing the first semiconducting layer and the second semiconducting layer except for predetermined portions is further carried out.

13. The method of manufacturing a field-effect transistor according to claim 12,

wherein, after carrying out the sixth step, a seventh step of forming a source electrode to be connected to the first semiconducting layer and the second semiconducting layer as well as a drain electrode to be connected to the first semiconducting layer and the second semiconducting layer is further carried out.

14. The method of manufacturing a field-effect transistor according to claim 8,

wherein the first semiconducting layer further contains Zn element, Sn (tin) element, Ge (germanium) element or Si (silicon) element.

15. The method of manufacturing a field-effect transistor according to claim 8,

wherein the second semiconducting layer further contains Sn element.