THIN FILM FET DEVICE AND METHOD FOR FORMING THE SAME

• US 20120280235A1
• Filed: 05/02/2012
• Published: 11/08/2012
• Est. Priority Date: 05/03/2011
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: LI, Yanzhao
• Application Number:
  US13/461,905
• Publication Number:
  US 20120280235A1
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795

Abstract

A thin film FET device and a method of forming the same are disclosed. The method comprises: etching a single crystal silicon thin film layer on an insulating thin film layer of an SOI substrate, wherein the etched single crystal silicon thin film layer is used as a channel; forming a gate insulating layer on the SOI substrate that has the single crystal silicon channel formed thereon; and forming a gate electrode, a drain electrode, and a source electrode.

Claims

1. A method of forming a thin film field effect transistor (FET) device, comprising:

etching a single crystal silicon thin film layer on an insulating thin film layer of an silicon-on-insulator (SOI) substrate, wherein the etched single crystal silicon thin film layer is used as a channel;

forming a gate insulating layer on the SOI substrate that has the single crystal silicon channel formed thereon; and

forming a gate electrode, a drain electrode, and a source electrode.

2. The method according to claim 1, wherein the step of forming the gate electrode, the drain electrode, and the source electrode comprises:

forming on the gate insulating layer a metal gate electrode, or using a single crystal silicon underlayer contained by the SOI substrate and located under the insulating thin film layer as the gate electrode;

covering the gate insulating layer and the metal gate or the gate insulating layer with a passivation layer;

forming a drain electrode and a source electrode at selected locations of the passivation layer, which penetrate the gate insulating layer and the passivation layer to contact the single crystal silicon thin film layer.

3. The method according to claim 1, wherein the step of etching the single crystal silicon thin film layer on the insulating thin film layer of the SOI substrate, wherein the etched single crystal silicon thin film layer is used as the channel, comprises:

applying photoresist on the single crystal silicon thin film layer of the SOI substrate, performing exposing and developing in regions outside those in which the channel is to be formed, etching the single crystal silicon thin film layer exposed after the exposing and developing, wherein the etched single crystal silicon thin film layer is used as the channel.

4. The method according to claim 3, wherein the single crystal silicon underlayer and the single crystal silicon thin film layer included in the SOI substrate both are a n-type silicon material or a p-type silicon material.

5. The method according to claim 4, further comprising:

doping the n-type silicon material or the p-type silicon material at a surface layer of the single crystal silicon thin film layer to transform them into a p-type silicon material or a n-type silicon material.

6. The method according to claim 1, wherein the step of forming the gate insulating layer on the SOI substrate that has the single crystal silicon channel formed thereon comprises:

depositing silicon oxide on the etched SOI substrate to form the gate insulating layer;

or thermally oxidizing the etched SOI substrate to form the gate insulating layer, wherein the thermally oxidizing is performed at a temperature of 400-1500°

C. in an atmosphere of oxygen;

or

depositing silicon nitride on the etched SOI substrate to form the gate insulating layer.

7. The method according to claim 2, wherein the step of forming on the gate insulating layer the metal gate comprises:

sputtering a gate metal onto the gate insulating layer in a vacuum with a pressure not higher than 10 Pa to form a gate metal layer;

applying photoresist onto the gate metal layer, exposing and developing regions outside those in which the metal gate electrode needs to be formed, etching the gate metal layer exposed after the exposing and developing, in which the etched gate metal layer is used as the metal gate electrode.

8. The method according to claim 2, wherein the step of covering the gate insulating layer and the metal gate or the gate insulating layer with the passivation layer comprises:

depositing silicon nitride on the gate insulating layer and the metal gate or on the gate insulating layer using plasma enhanced chemical vapor deposition to form the passivation layer.

9. The method according to claim 2, wherein the step of forming the drain electrode and the source electrode at the selected locations of the passivation layer, which penetrate the gate insulating layer and the passivation layer to contact the single crystal silicon thin film layer, comprises:

applying photoresist to the passivation layer, exposing and developing regions in which the source and drain electrodes need to be formed, etching the passivation layer exposed after the exposing and developing to form depositing holes for the source and drain electrodes which penetrate the gate insulating layer and the passivation layer; and

depositing electrode metal in the depositing holes using sputtering to form the source and drain electrodes that contact the single crystal silicon thin film layer.

10. The method according to claim 9, after forming the source and drain electrodes, further comprising:

depositing an insulating isolation layer as a pixel region in a region except for the source electrode on the ourter surface of the SOI substrate having the source and drain electrodes formed thereon; and

depositing an electrode of indium tin oxide as an anode in the pixel region, which contacts the source electrode through a contact hole, and forming an organic light-emitting diode OLED device.

11. A thin film thin film transistor (FET) device comprising:

an silicon-on-insulator (SOI) substrate including a single crystal silicon underlayer, an insulating thin film layer, and a single crystal silicon thin film layer, wherein after being etched, the single crystal silicon thin film layer forms a channel;

a gate insulating layer covering the SOI substrate; and

a gate electrode, a source, and a drain electrode.

12. The thin film FET device according to claim 11, wherein the gate is a metal gate formed on the gate insulating layer, or the single crystal silicon underlayer included in the SOI substrate is used as the gate electrode;

the source electrode and the drain electrode are located at selected locations of a passivation layer, penetrate the gate insulating layer and the passivation layer, and contact the single crystal silicon thin film layer, the passivation layer covering the gate insulating layer and the metal gate or the gate insulating layer.

13. The thin film FET device according to claim 11, wherein the single crystal silicon underlayer has a thickness of 100-500 μ

m, the insulating thin film layer has a thickness of 5 nm-4 μ

m, and the single crystal silicon thin film layer has a thickness of 5-1500 nm.

14. The thin film FET device according to claim 13, wherein the the single crystal silicon underlayer and the single crystal silicon thin film layer included in the SOI substrate both are a n-type or p-type silicon material.

15. The thin film FET device according to claim 14, wherein a surface layer of the single crystal silicon thin film layer is a p-type silicon material or a n-type silicon material, which is formed by doping the n-type silicon material or the p-type silicon material.

16. The thin film FET device according to claim 11, wherein the thickness of the gate insulating layer is of 1-250 nm.

17. The thin film FET device according to claim 12, wherein a gate metal of the metal gate comprises Mo, Al, or Cr, and the metal gate has a thickness of 30-1000 nm.

18. The thin film FET device according to claim 12, wherein the passivation layer has a thickness of 30-1500 nm.

19. The thin film FET device according to claim 12, wherein electrode metal material of the source electrode and the drain electrode comprises Mo, Al, or Cr, and the source electrode and the drain electrode have thicknesses of 30-1000 nm.

20. The thin film FET device according to claim 12, further comprising:

an insulating isolation layer, which is formed using deposition process in a region except for the source electrode on the outer surface of the SOI substrate having the source and drain electrodes formed thereon; and

an electrode of indium tin oxide as anode, which is formed in a region except for the source electrode by deposition process, and contacts the source region via a contact hole.