THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE THIN FILM TRANSISTOR ARRAY SUBSTRATE

• US 20120280239A1
• Filed: 05/04/2012
• Published: 11/08/2012
• Est. Priority Date: 05/06/2011
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: LIU, Xiang, XUE, Jianshe
• Application Number:
  US13/464,094
• Publication Number:
  US 20120280239A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present disclosed technology is related to a TFT array substrate and a method for fabricating the TFT array substrate. The method may comprise: depositing a transparent conductive film layer and a source-drain metal layer in this order on a base substrate, and forming source electrodes, drain electrodes, data scan lines and transparent pixel electrodes by a first pattering process, with the transparent conductive film layer being left under the source electrodes, the drain electrodes and the data scan lines; on the resultant substrate, depositing a semiconductor layer and forming a patterned semiconductor layer by a second pattering process; and on the resultant substrate, depositing a gate insulator and a gate metal film in this order, and forming gate electrodes and gate scan lines by a third pattering process, the gate electrodes being located over the patterned semiconductor layer.

Claims

1. A method for fabricating a thin film transistor (TFT) array substrate, comprising the steps of:

(1) depositing a transparent conductive film layer and a source-drain metal layer in this order on a base substrate, and forming source electrodes, drain electrodes, data scan lines and transparent pixel electrodes by a first pattering process, with the transparent conductive film layer being left under the source electrodes, the drain electrodes and the data scan lines;

(2) on the substrate obtained from the step (1), depositing a semiconductor layer and forming a patterned semiconductor layer by a second pattering process; and

(3) on the substrate obtained from the step (2), depositing a gate insulator and a gate metal film in this order, and forming gate electrodes and gate scan lines by a third pattering process, the gate electrodes being located over the patterned semiconductor layer.

2. The method for fabricating the TFT array substrate according to claim 1, wherein before depositing the transparent conductive film layer and the source-drain metal layer on the base substrate, the method further comprises:

forming a protective layer on the base substrate.

3. The method for fabricating the TFT array substrate according to claim 1, wherein before depositing the transparent conductive film layer and the source-drain metal layer on the base substrate, the method further comprises:

forming a black matrix and forming a variety of color filters on the base substrate.

4. The method for fabricating the TFT array substrate according to claim 3, wherein after forming the black matrix and forming the variety of color filters on the base substrate, and before depositing the transparent conductive film layer and the source-drain metal layer on the base substrate, the method further comprises:

forming an organic flattening layer on the base substrate, and then forming a protective layer on the organic flattening layer.

5. The method for fabricating the TFT array substrate according to claim 1, wherein the depositing the gate insulator comprises:

depositing two gate insulating sub-layers successively by using a plasma enhanced chemical vapor deposition (PECVD) method, wherein one of the sub-layers which contacts the semiconductor layer is deposited at a lower speed than that of the other sub-layer.

6. The method for fabricating the TFT array substrate according to claim 2, wherein the depositing the gate insulator comprises:

depositing two gate insulating sub-layers successively by using a plasma enhanced chemical vapor deposition (PECVD) process, wherein one of the sub-layers which contacts the semiconductor layer is deposited at a lower speed than that of the other sub-layer.

7. The method for fabricating the TFT array substrate according to claim 3, wherein the depositing the gate insulator comprises:

depositing two gate insulating sub-layers successively by using a plasma enhanced chemical vapor deposition (PECVD) process, wherein one of the sub-layers which contacts the semiconductor layer is deposited at a lower speed than that of the other sub-layer.

8. The method for fabricating the TFT array substrate according to claim 4, wherein the depositing the gate insulator comprises:

depositing two gate insulating sub-layers successively by using a plasma enhanced chemical vapor deposition (PECVD) process, wherein one of the sub-layers which contacts the semiconductor layer is deposited at a lower speed than that of the other sub-layer.

9. The method for fabricating the TFT array substrate according to claim 1, wherein the forming of the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by the first pattering process comprises:

forming the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by exposing with a gray tone or half tone mask, developing and several etching processes.

10. The method for fabricating the TFT array substrate according to claim 2, wherein the forming of the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by the first pattering process comprises:

forming the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by exposing with a gray tone or half tone mask, developing and several etching processes.

11. The method for fabricating the TFT array substrate according to claim 3, wherein the forming of the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by the first pattering process comprises:

forming the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by exposing with a gray tone or half tone mask, developing and several etching processes.

12. The method for fabricating the TFT array substrate according to claim 4, wherein the forming of the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by the first pattering process comprises:

forming the source electrodes, the drain electrodes, the data scan lines and the transparent pixel electrodes by exposing with a gray tone or half tone mask, developing and several etching processes.

13. A thin film transistor (TFT) array substrate comprising:

a base substrate;

transparent pixel electrodes provided above the base substrate;

source electrodes, drain electrodes and data scan lines with the transparent conductive film for forming the transparent pixel electrodes being left under them;

a patterned semiconductor layer formed on the source electrodes and the drain electrodes;

a gate insulator covering the patterned semiconductor layer; and

gate electrodes and gate scan lines formed on the gate insulator and located over the patterned semiconductor layer.

14. The TFT array substrate according to claim 13, wherein the array substrate further comprises a protective layer formed on the array substrate, and the transparent pixel electrodes are formed on the protective layer.

15. The TFT array substrate according to claim 13, wherein the array substrate further comprises a black matrix and a variety of color filters, both of which are formed on the array substrate, and the transparent pixel electrodes are formed on the black matrix and the color filters.

16. The TFT array substrate according to claim 15, wherein the array substrate further comprises an organic flattening layer and a protective layer, both of which are formed on the black matrix and the color filters, and the organic flattening layer is provided on the base substrate, and the protective layer is deposited on the organic flatting layer.