Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same

• US 20120280299A1
• Filed: 03/08/2012
• Published: 11/08/2012
• Est. Priority Date: 05/04/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seol, Kwang Soo, Park, Youngwoo, Yun, Jang-Gn
• Granted Patent: US 9,099,347 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

Claims

1. A three-dimensional semiconductor memory device, comprising:

an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, at least an uppermost electrode of the electrodes being divided into a plurality of physically isolated segments arranged in the first direction;

vertical active patterns that penetrate the electrode structure; and

an electrode-dielectric layer disposed between each of the vertical active patterns and each of the electrodes,

wherein the segments of the uppermost electrode are electrically connected to each other.

2. The device of claim 1, wherein a lowermost electrode of the electrodes in the electrode structure is not divided into segments.

3. The device of claim 1, wherein the substrate includes a plurality of sub-cell regions and a buffer region disposed between the sub-cell regions, and the electrode structure crosses over the sub-cell regions and the buffer region;

wherein the segments of the uppermost electrode are disposed in the sub-cell regions, respectively;

wherein the segments of the uppermost electrode include extensions extending into the buffer region, respectively; and

wherein a cutting region is provided in the buffer region between the segments of the uppermost electrode.

4. The device of claim 3, further comprising:

a capping dielectric pattern in the cutting region, wherein the capping dielectric pattern provides the physical isolation between the segments of the uppermost electrode.

5. The device of claim 3, wherein the uppermost electrode comprises a string selection electrode;

wherein the electrodes include cell electrodes which are stacked and are disposed under the string selection electrode;

wherein at least uppermost cell electrode of the cell electrodes is divided into a plurality of segments arranged in the one direction; and

wherein the cutting region extends downwardly between the segments of the uppermost cell electrode.

6. The device of claim 5, wherein the cutting region includes an inner sidewall having a stepped shape.

7. The device of claim 5, further comprising:

a string join interconnection disposed in the buffer region and electrically connecting the segments of the string selection electrode to each other; and

a floor-join interconnection disposed in the buffer region and electrically connecting the segments of the uppermost cell electrode to each other.

8. The device of claim 7, wherein each of a plurality of cell electrodes is divided into physically isolated segments arranged in the one direction;

wherein the floor-join interconnection comprises a plurality of floor-join interconnections, a number of the floor-join interconnections corresponding to a number of the divided cell electrodes; and

wherein the plurality of the floor-join interconnections are disposed on the electrode structure and are respectively disposed different levels from each other with respect to a top surface of the substrate.

9. The device of claim 7, wherein the electrode structure is provided in a plural number to extend in parallel to each other;

wherein each of a plurality of cell electrodes that is stacked in each of the electrode structures is divided into segments arranged in the first direction;

wherein the floor-join interconnection comprises a plurality of floor-join interconnections disposed on the electrode structures, respectively;

wherein each of the floor-join interconnections electrically connects segments of one of the divided cell electrodes in the electrode structure under each of the floor interconnections to each other; and

wherein the segments connected to one of the floor-join interconnections are disposed at a different level from the segments connected to others of the floor-join interconnections.

10. The device of claim 9, wherein the substrate further includes a first edge region and a second edge region, and the sub-cell regions and the buffer region are disposed between the first edge region and the second edge region;

wherein the cell electrodes being stacked in each of the electrode structures include first electrode pads having a stepped structure and being disposed in the first edged region, and second electrode pads having a stepped structure and being disposed in the second edge region;

wherein the first electrode pads of the cell electrodes, which are respectively included in the plurality of the electrode structures and are disposed at the same level, are electrically connected to each other; and

wherein the second electrode pads of the cell electrodes, which are respectively included in the plurality of the electrode structures and are disposed at the same level, are electrically connected to each other.

11-15. -15. (canceled)

16. A three-dimensional semiconductor memory device, comprising:

a substrate;

an electrode structure on the substrate, the electrode structure including a plurality of electrode layers and a plurality of insulating pattern layers that are stacked in an alternating manner on the substrate in a vertical direction, wherein at least an uppermost electrode layer of the electrode structure is divided into first and second horizontal segments;

a plurality of vertical active patterns that extend through the electrode structure in the vertical direction; and

a plurality of dielectric layers between the vertical active patterns and respective ones of the electrode layers;

wherein the first and second horizontal segments of the uppermost electrode are electrically connected to each other.