STRUCTURE AND METHOD FOR FORMING SHIELDED GATE TRENCH FET WITH MULTIPLE CHANNELS

• US 20120280312A1
• Filed: 07/19/2012
• Published: 11/08/2012
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: James Pan
• Inventors: Pan, James
• Granted Patent: US 9,224,853 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.

Claims

1. An apparatus, comprising:

a pair of trenches extending into a semiconductor region of a first conductivity type;

a shield electrode disposed in a trench from the pair of trenches;

a gate electrode disposed above and insulated from the shield electrode;

a source region of the first conductivity type associated with the trench;

a first well region of a second conductivity type disposed in the semiconductor region between the pair of trenches and below the source region, the first well region abutting a sidewall of the trench from the pair of trenches, the second conductivity type being opposite the first conductivity type;

a second well region of the second conductivity type disposed in the semiconductor region between the pair of trenches; and

a third well region of the first conductivity type disposed between the first well region and the second well region.

2. The apparatus of claim 1, wherein the first well region, the second well region, and the third well region are associated with the shield electrode.

3. The apparatus of claim 1, wherein the first well region, the second well region, and the third well region are disposed lateral to the shield electrode.

4. The apparatus of claim 1, wherein the shield electrode is formed relative to the first well region and the second well region such that a channel is formed in each of the first well region and the second well region when a voltage is applied to the shield electrode.

5. The apparatus of claim 1, wherein the shield electrode is a first shield electrode,

the apparatus further comprising:

a second shield electrode electrically insulated from the first shield electrode.

6. The apparatus of claim 1, wherein the shield electrode is a first shield electrode, the first well region, the second well region, and the third well region are disposed lateral to the first shield electrode,

the apparatus further comprising:

a second shield electrode electrically insulated from the first shield electrode.

7. The apparatus of claim 1, wherein the shield electrode is a first shield electrode,

the apparatus further comprising:

a second shield electrode;

a dielectric disposed in the trench between the first shield electrode and the second shield electrode, the second shield electrode is electrically coupled to the first shield electrode.

8. An apparatus, comprising:

a trench extending into a semiconductor region of a first conductivity type;

an electrode disposed in the trench;

a source region of the first conductivity type abutting a sidewall of the trench;

a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode, the second conductivity type being opposite the first conductivity type;

a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench; and

a third well region of the first conductivity type disposed between the first well region and the second well region.

9. The apparatus of claim 8, wherein the first well region, the second well region, and the third well region are associated with the electrode.

10. The apparatus of claim 8, wherein the electrode is a shield electrode, the shield electrode is formed relative to the first well region and the second well region such that a channel is formed in each of the first well region and the second well region when a voltage is applied to the shield electrode.

11. The apparatus of claim 8, wherein the electrode is a shield electrode,

the apparatus further comprising:

a gate electrode disposed above and insulated from at least a portion of the shield electrode; and

a fourth well region disposed between the first well region and source well region, the fourth well region being disposed lateral to the gate electrode.

12. The apparatus of claim 8, wherein the electrode is a gate electrode,

the apparatus further comprising:

a shield electrode disposed below and insulated from at least a portion of the gate electrode, the second well region being disposed lateral to the shield electrode.

13. The apparatus of claim 8, wherein the electrode is a first shield electrode,

the apparatus further comprising:

a second shield electrode electrically insulated from the first shield electrode.

14. The apparatus of claim 8, wherein the electrode is a first shield electrode, the first well region, the second well region, and the third well region are disposed lateral to the first shield electrode,

the apparatus further comprising:

a second shield electrode electrically insulated from the first shield electrode.

15. The apparatus of claim 8, wherein the electrode is a first shield electrode,

the apparatus further comprising:

a second shield electrode;

a dielectric disposed in the trench between the first shield electrode and the second shield electrode, the second shield electrode is electrically coupled to the first shield electrode.

16. An apparatus, comprising:

a trench extending into a semiconductor region of a first conductivity type;

a shield electrode disposed in the trench;

a gate electrode disposed above and insulated from the shield electrode;

a source region of the first conductivity type abutting a sidewall of the trench;

a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench, the second conductivity type being opposite the first conductivity type;

a second well region of the second conductivity type disposed in the semiconductor region; and

a third well region of the first conductivity type disposed between the first well region and the second well region.

17. The apparatus of claim 16, wherein the first well region, the second well region, and the third well region are disposed lateral to the shield electrode.

18. The apparatus of claim 16, wherein the shield electrode is formed relative to the first well region and the second well region such that a channel is formed in each of the first well region and the second well region when a voltage is applied to the shield electrode.

19. The apparatus of claim 16, further comprising:

a heavy body region of the second conductivity type in contact with the source region.

20. The apparatus of claim 16, wherein the gate electrode and the shield electrode are positioned relative to the first well region and second well region such that a channel is formed in each of the first well region and the second well regions when the apparatus is biased in the on state.