METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES

• US 20120280354A1
• Filed: 05/05/2011
• Published: 11/08/2012
• Est. Priority Date: 05/05/2011
• Status: Abandoned Application

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: MOROZ, VICTOR, LIN, XI-WEI
• Application Number:
  US13/101,665
• Publication Number:
  US 20120280354A1
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

Claims

1. An article of manufacture comprising:

a machine readable data storage medium storing a design entry for an integrated circuit, the design entry including;

a layout comprising a plurality of lines to be formed in a material layer during fabrication of an integrated circuit device; and

a mask layer to be formed overlying the material layer during fabrication of the plurality of lines, the mask layer specifying an intermediate mask element having a single edge for fabricating the entire plurality of lines.

2. The article of manufacture of claim 1, wherein lines in the plurality of lines have substantially congruent shapes.

3. The article of manufacture of claim 1, wherein adjacent lines in the plurality of lines are separated from one another in a direction normal to the single edge of the mask element.

4. The article of manufacture of claim 1, wherein the single edge of the mask layer is aligned with an edge of a particular line in the plurality of lines.

5. The article of manufacture of claim 1, wherein the single edge of the mask layer has a contour representative of shapes of the entire plurality of lines.

6. The article of manufacture of claim 1, wherein the single edge of the mask layer has a contour representative of shapes of each of the plurality of lines.

7. The article of manufacture of claim 1, wherein:

the physical layout further comprises a second plurality of lines in the material layer; and

the mask layer has a second single edge for fabricating the entire second plurality of lines.

8. A method for manufacturing an integrated circuit device, the method comprising:

providing a material layer;

forming a first set of sidewall spacers and a second set of sidewalls spacers on the material layer, the first and second sets of sidewall spacers arranged in an alternating fashion, so that adjacent sidewall spacers in the first set are separated by a single sidewall spacer in the second set, and adjacent sidewall spacers in the second set are separated by a single sidewall spacer in the first set; and

processing the first and second sets of sidewall spacers to form a plurality of lines at locations defined by the first set of sidewall spacers.

9. The method of claim 8, wherein processing the first and second sets of sidewall spacers comprises etching the material layer using the first set of sidewall spacers as etch masks, thereby forming a plurality of trenches in the material layer at locations defined by the second set of sidewall spacers, to form the plurality of lines in the material layer, adjacent lines in the plurality of lines separated by a corresponding trench in the plurality of trenches.

10. The method of claim 8, wherein processing the first and second sets of sidewall spacers comprises:

selectively removing the first set of sidewall spacers to expose a top surface of the material layer and leave openings between adjacent sidewall spacers in the second set of sidewall spacers; and

forming a second material layer within the openings to form the plurality of lines on the top surface of the material layer.

11. The method of claim 10, wherein forming the second material layer comprises performing an epitaxial process.

12. The method of claim 8, wherein forming the first and second sets of sidewall spacers includes:

forming an intermediate mask element on the material layer, the intermediate mask element having a sidewall surface;

forming a first sidewall spacer of the first set on the sidewall surface of the intermediate element, the first sidewall spacer of the first set having opposing first and second sidewall surfaces;

removing the intermediate element; and

forming first and second sidewall spacers of the second set on the respective first and second sidewall surfaces of the first sidewall spacer of the first set.

13. The method of claim 12, wherein the intermediate mask element is formed using a lithographic process.

14. The method of claim 12, wherein forming the first and second sets of sidewall spacers further includes:

forming a second sidewall spacer of the first set on a side surface of the first sidewall spacer of the second set; and

forming a third sidewall spacer of the first set on a side surface of the second sidewall spacer of the second set.

15. The method of claim 8, further comprising forming a third set of sidewall spacers and a fourth set of sidewall spacers on the material layer, the third and fourth sets of sidewall spacers arranged in an alternating fashion, so that adjacent sidewall spacers in the third set are separated by a single sidewall spacer in the fourth set, and adjacent sidewall spacers in the fourth set are separated by a single sidewall spacer in the third set, and wherein the processing further includes processing the third and fourth sets of sidewall spacers to form a second plurality of lines at locations defined by the third set of sidewall spacers.

16. The method of claim 8, wherein lines in the plurality of lines have substantially the same width.

17. The method of claim 8, wherein adjacent lines in the plurality of lines are separated by substantially the same separation width across the plurality of lines.

18. The method of claim 8, wherein the lines in the plurality of lines have a width that varies across the plurality of lines by less than 10%.

19. The method of claim 8, wherein the lines in the plurality of lines have a width less than or equal to 15 nm.

20. An integrated circuit device comprising:

a first plurality of lines separated from a second plurality of lines by a minimum spacing at least twice a width of a particular line in the first plurality of lines;

each line in the first plurality of lines having a first line width roughness and a first line edge roughness less than the first line width roughness;

each line in the second plurality of lines having a second line width roughness and a second line edge roughness less than the second line width roughness; and

all the lines in the first plurality of lines having a longitudinal curvature different from each of the lines in the second plurality of lines.