SEMICONDUCTOR CHIP, MEMORY CHIP, SEMICONDUCTOR PACKAGE AND MEMORY SYSTEM

• US 20120281449A1
• Filed: 05/02/2012
• Published: 11/08/2012
• Est. Priority Date: 05/03/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Boseong
• Granted Patent: US 9,286,950 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group

Abstract

A semiconductor chip includes a plurality of signal and power pads; and a plurality of chip selection pads, wherein at least one of the plurality of chip selection pads includes a normal pad and an inverse pad.

Claims

1. A semiconductor chip comprising:

a plurality of signal and power pads; and

a plurality of chip selection pads,

wherein at least one of the plurality of chip selection pads comprises a normal pad and an inverse pad.

2. The semiconductor chip of claim 1, wherein the semiconductor chip is a memory chip.

3. The semiconductor chip of claim 1, wherein the semiconductor chip is a memory controller chip.

4. The semiconductor chip of claim 1, wherein the normal pad of the at least one of the plurality of chip selection pads is connected with a first conduction line and the inverse pad of the at least one of the plurality of chip selection pads is connected with a second conduction line, the first conduction line and the second conduction line are connected in common with a third conduction line.

5. The semiconductor chip of claim 4, further comprising:

a logic gate configured to perform an AND operation with respect to the third conduction line of the plurality of chip selection pads, and

wherein the semiconductor chip is activated or inactivated according to an output of the logic gate.

6. A memory chip comprising:

at least one chip selection solder bump;

at least one through silicon via electrically connected with the at least one chip selection solder bump;

first and second fuses electrically connected with the at least one through silicon via;

normal and inverse inputs, at least one of the normal and inverse inputs is electrically connected with the first and second fuses; and

at least one chip selection pad electrically connected with the first and second fuses.

7. A memory chip comprising:

a plurality of signal and power pads;

a plurality of chip selection pads; and

a logic gate configured to operate the plurality of chip selection pads,

wherein the memory chip is activated or inactivated according to an output of the logic gate.

8. A semiconductor package comprising:

first and second memory chips configured to be stacked,

wherein at least one of the first memory chips and at least one of the second memory chips comprises a plurality of signal and power pads and a plurality of chip selection pads.

9. The semiconductor package of claim 8, wherein at least one of the plurality of chip selection pads includes a normal pad and an inverse pad.

10. The semiconductor package of claim 9, wherein the first and second memory chips are stacked in a cascade shape.

11. The semiconductor package of claim 10, wherein one of the normal pad and the inverse pad of a first chip selection pad of a first memory chip is connected with a first conduction line and the other one of the normal pad and the inverse pad of the first selection pad of the first memory chip is floated.

12. The semiconductor package of claim 11, wherein one of the normal pad and the inverse pad of a first chip selection pad of a second memory chip is connected with the first conduction line and the other one of the normal pad and the inverse pad of the first selection pad of the second memory chip is floated.

13. The semiconductor package of claim 11, wherein one of the normal pad and the inverse pad of a second chip selection pad of the first memory chip is connected with a second conduction line, different from the first conduction line, and the other one of the normal pad and the inverse pad of the second chip selection pad of the first memory chip is floated.

14. The semiconductor package of claim 11, further comprising:

a controller chip configured to control the first and second memory chips,

wherein the controller chip comprises a plurality of second signal and power pads, at least one of the plurality of second signal and power pads corresponds with the plurality of signal and power pads; and

a plurality of control chip selection pads, at least one of the plurality of control chip selection pads corresponds with the plurality of chip selection pads, the first conduction line is connected with one of the plurality of control chip selection pads.

15. The semiconductor package of claim 14, wherein the controller chip is configured to select the first and second memory chips by controlling output signals of the plurality of control chip selection pads.

16. The semiconductor package of claim 11, further comprising:

a plurality of signal and power input and output nodes, at least one of the plurality of signal and power input and output nodes corresponds with the plurality of signal and power pads; and

a plurality of chip selection nodes, at least one of the plurality of chip selection nodes corresponds with the plurality of chip selection pads,

the first conduction line is connected with one of the plurality of chip selection nodes.

17. The semiconductor package of claim 16, wherein the plurality of chip selection nodes are a plurality of pins or a plurality of solder balls.

18. The semiconductor package of claim 9, wherein the first and second memory chips are stacked in a vertical pillar shape.

19. The semiconductor package of claim 18, further comprising:

a controller chip configured to control the first and second memory chips,

wherein the controller chip comprises a plurality of second signal and power pads, at least one of the plurality of second signal and power pads corresponds with the plurality of signal and power pads; and

a plurality of control chip selection pads, at least one of the plurality of control chip selection pads corresponds with the plurality of chip selection pads.

20. The semiconductor package of claim 19, wherein one of the normal pad and the inverse pad of a first chip selection pad of a first memory chip is electrically connected with a first control chip selection pad of the plurality of control chip selection pads and the other one of the normal pad and the inverse pad of the first chip selection pad of the first memory chip is floated.

21. The semiconductor package of claim 20, wherein one of the normal pad and the inverse pad of a first chip selection pad of a second memory chip is electrically connected with the first control chip selection pad and the other one of the normal pad and the inverse pad of the first chip selection pad of the second memory chip is floated.

22. The semiconductor package of claim 20, wherein one of the normal pad and the inverse pad of a second chip selection pad of the first memory chip is electrically connected with a second control chip selection pad, different from the first control chip selection pad, of the plurality of control chip selection pads and the other one of the normal pad and the inverse pad of the second chip selection pad of the first memory chip is floated.

23. The semiconductor package of claim 18, further comprising:

a plurality of signal and power input and output nodes, at least one of the plurality of signal and power input and output nodes corresponds with the plurality of signal and power pads; and

a plurality of chip selection nodes, at least one of the plurality of chip selection nodes corresponds with the plurality of chip selection pads.

24. The semiconductor package of claim 23, wherein one of the normal pad and the inverse pad of a first chip selection pad of a first memory chip is electrically connected with a first chip selection node of the plurality of chip selection nodes and the other one of the normal pad and the inverse pad of the first chip selection pad of the first memory chip is floated.

25. The semiconductor package of claim 24, wherein one of the normal pad and the inverse pad of a first chip selection pad of a second memory chip is electrically connected with the first chip selection node and the other one of the normal pad and the inverse pad of the first chip selection pad of the second memory chip is floated.

26. The semiconductor package of claim 24, wherein one of the normal pad and the inverse pad of a second chip selection pad of the first memory chip is electrically connected with a second chip selection node, different from the first chip selection node, of the plurality of chip selection nodes and the other one of the normal pad and the inverse pad of the second chip selection pad of the first memory chip is floated.

27. The semiconductor package of claim 8, wherein the first and second memory chips are stacked in a cascade shape.

28. The semiconductor package of claim 27, wherein a part of a first chip selection pad of the first and second memory chips is connected in common with a first conduction line and a remaining part of the first chip selection pad is connected in common with a second conduction line.

29. The semiconductor package of claim 28, further comprising:

a controller chip configured to control the first and second memory chips,

wherein the controller chip comprises a plurality of control chip selection pads, at least one of the plurality of controller chip selection pads corresponds with the plurality of chip selection pads, at least one of the plurality of control chip selection pads comprises a normal pad and an inverse pad.

30. The semiconductor package of claim 29, wherein the first conduction line is electrically connected with the normal pad of a first control chip selection pad of the plurality of control chip selection pads and the second conduction line is electrically connected with the inverse pad of the first control chip selection pad.

31. The semiconductor package of claim 27, further comprising:

chip selection nodes, at least one of the chip selection nodes corresponds with the plurality of chip selection pads,

wherein at least one of the chip selection nodes comprises a normal node and an inverse node, and

wherein a first conduction line is electrically connected with the normal node of a first chip selection node of the chip selection nodes and a second conduction line is electrically connected with the inverse node of the first chip selection node.

32. The semiconductor package of claim 8, wherein the first and second memory chips are stacked in a vertical pillar shape.

33. The semiconductor package of claim 32, further comprising:

a controller chip configured to control the first and second memory chips,

wherein the controller chip comprises a plurality of control chip selection pads, at least one of the plurality of control chip selection pads corresponds with the plurality of chip selection pads, at least one of the plurality of control chip selection pads comprises a normal pad and an inverse pad.

34. The semiconductor package of claim 33, wherein a part of a first chip selection pad of the first and second memory chips is electrically connected with the normal pad of a first control chip selection pad of the controller chip via a plurality of first conduction lines and a remaining part of the first chip selection pad of the first and second memory chips is electrically connected with the inverse pad of the first control chip selection pad via a plurality of second conduction lines.

35. The semiconductor package of claim 32, further comprising:

a plurality of chip selection nodes, at least one of the plurality of chip selection nodes corresponds with the plurality of chip selection pads,

wherein at least one of the chip selection nodes includes a normal node and an inverse node.

36. The semiconductor package of claim 35, wherein a part of a first chip selection node of the first and second memory chips is electrically connected with the normal pad of the first chip selection node of the chip selection nodes via a plurality of first conduction lines and a remaining part of the first chip selection node of the first and second memory chips is electrically connected with the inverse pad of the first chip selection node via a plurality of second conduction lines.

37. The semiconductor package of claim 8, wherein the first memory chip comprises:

a plurality of chip selection solder bumps;

a plurality of through silicon vias, at least one of the plurality of through silicon vias is electrically connected with the plurality of chip selection solder bumps and a plurality of chip selection pads;

first and second fuses electrically connected with a through silicon via of the plurality of through silicon vias; and

normal and inverse inputs, at least one of the normal and inverse inputs is electrically connected with the first and second fuses.

38. The semiconductor package of claim 37, wherein a second memory chip has a same structure as a first memory chip,

wherein at least one or more chip selection solder bumps of the second memory chip are connected with at least one or more chip selection pads of the first memory chip.

39. The semiconductor package of claim 37, wherein one of the first and second fuses connected with the through silicon via of the first memory chip is cut and the other one of the first and second fuses maintains an electric connection state.

40. A semiconductor package comprising:

a controller chip configured to control a memory;

a plurality of signal and power nodes electrically connected with a plurality of signal and power pads of the controller chip; and

a plurality of chip selection nodes electrically connected with a plurality of chip selection pads of the controller chip,

wherein a chip selection pad of the plurality of chip selection nodes comprises a normal pad and an inverse pad, and

wherein the chip selection node of the plurality of chip selection nodes comprises the normal node and the inverse node, at least one of the normal node and the inverse node is connected with the normal pad and the inverse pad.

41. A memory controller chip comprising:

a plurality of signal and power pads; and

a plurality of chip selection pads,

wherein at least one of the chip selection pads is independently controlled to have a logically high or a logically low value, and

wherein a combination of the chip selection pads is output as a chip selection signal.

42. A memory system comprising:

first and second memory chips configured to be stacked; and

a memory controller chip configured to control the first and second memory chips,

wherein at least one of the first and second memory chips is configured to communicate with the memory controller chip via a plurality of signal and power pads and a plurality of chip selection pads.

43. The memory system of claim 42, wherein the first and second memory chips and the memory controller chip constitute a memory card.

44. The memory system of claim 42, wherein the first and second memory chips and the memory controller chip constitute a solid state drive.

45. The memory system of claim 42, wherein the first and second memory chips and the memory controller chip form a single package.

46. The memory system of claim 42, wherein the first and second memory chips form a memory package and the memory controller chip forms a controller package.

47. A solid state drive comprising:

a substrate;

a plurality of memory packages;

a controller package; and

a connector.

48. The solid state drive of claim 47, wherein at least one of the plurality of memory packages comprises first and second memory chips, the first and second memory chips are configured to be stacked.

49. The solid state drive of claim 47, wherein the controller package comprises a controller chip, the controller chip configured to select the at least one of the plurality of memory packages using a smaller number of signals than a total number of signals of the at least one of the plurality of memory packages.

50. The solid state drive of claim 47, wherein at least one of the plurality of memory packages and the controller package communicates with an external device via the connector.