Memory Page Buffer

• US 20120281471A1
• Filed: 05/05/2011
• Published: 11/08/2012
• Est. Priority Date: 05/05/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hung, Chun-Hsiung, Lo, Chi
• Granted Patent: US 8,432,746 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.

Claims

1. A memory method, comprising:

responsive to a second read instruction to perform a read operation on a second memory cell coupled to a bit line, the second read instruction after a first read instruction to perform the read operation on a first memory cell coupled to the bit line, performing;

applying a read bias arrangement to the second memory cell without discharging the bit line prior to applying the read bias arrangement.

2. The method of claim 1, wherein the first memory cell has a threshold voltage in a low magnitude threshold voltage distribution of a plurality of selectable threshold voltage distributions.

3. The method of claim 1, wherein the read bias arrangement causes the current to flow through a diode between the source line and the bit line, the diode preventing the current from flowing from the bit line to the source line.

4. The method of claim 1, wherein the first memory cell and the second memory cell are included in a 3D memory array.

5. The method of claim 1, the read bias arrangement reads a data value on the second memory cell based on whether current flows from a source line of the second memory cell to the bit line coupled to the second memory cell.

6. The method of claim 1, responsive to the second read instruction, further performing:

prior to applying the read bias arrangement, precharging the bit line.

7. The method of claim 1, responsive to the second read instruction, further performing:

prior to applying the read bias arrangement, precharging the bit line sufficiently, such that responsive to the second memory cell having a threshold voltage in a low magnitude threshold voltage distribution of a plurality of selectable threshold voltage distributions, the current fails to flow responsive to applying the read bias arrangement to the second memory cell.

8. The method of claim 1, responsive to the second read instruction, further performing:

applying a sequence of increasingly larger magnitude voltages to a gate of the second memory cell.

9. The method of claim 1, responsive to the second read instruction, further performing:

applying a sequence of increasingly larger magnitude gate voltages to a gate of the second memory cell, including;

responsive to a previous gate voltage of the sequence causing the current indicating that the data value on the second memory cell corresponds to no threshold voltage distribution having magnitudes lower than a magnitude of the previous gate voltage, applying a next gate voltage of the sequence to the gate of the second memory cell.

10. A memory device, comprising:

a plurality of memory cells including a first memory cell and a second memory cell;

a plurality of bit lines coupled to the memory cells, the plurality of bit lines including a bit line coupled to the first memory cell and the second memory cell; and

a plurality of source lines coupled to the memory cells, the plurality of source lines including a source line coupled to the second memory cell; and

control circuitry responsive to a second read instruction to perform a read operation on the second memory cell after a first read instruction to perform the read operation on the first memory cell, by performing;

the control circuitry applying a read bias arrangement to the second memory cell without discharging the bit line prior to applying the read bias arrangement.

11. The device of claim 10, wherein the first memory cell has a threshold voltage in a low magnitude threshold voltage distribution of a plurality of selectable threshold voltage distributions.

12. The device of claim 10, wherein the read bias arrangement causes the current to flow through a diode between the source line and the bit line, the diode preventing the current from flowing from the bit line to the source line.

13. The device of claim 10, wherein the first memory cell and the second memory cell are included in a 3D memory array.

14. The device of claim 10, wherein the first memory cell and the second memory cell are included in a multilevel cell memory array.

15. The device of claim 10, wherein the control circuitry, responsive to the second read instruction, further performs:

prior to applying the read bias arrangement, precharging the bit line.

16. The device of claim 10, wherein the control circuitry, responsive to the second read instruction, further performs:

prior to applying the read bias arrangement, precharging the bit line sufficiently, such that responsive to the second memory cell having a threshold voltage in a low magnitude threshold voltage distribution of a plurality of selectable threshold voltage distributions, the current fails to flow responsive to applying the read bias arrangement to the second memory cell.

17. The device of claim 10, wherein the control circuitry, responsive to the second read instruction, further performs:

applying a sequence of increasingly larger magnitude voltages to a gate of the second memory cell.

18. The device of claim 10, wherein the control circuitry, responsive to the second read instruction, further performs:

applying a sequence of increasingly larger magnitude gate voltages to a gate of the second memory cell, including;

responsive to a previous gate voltage of the sequence causing the current indicating that the data value on the second memory cell corresponds to no threshold voltage distribution having magnitudes lower than a magnitude of the previous gate voltage, applying a next gate voltage of the sequence to the gate of the second memory cell.

19. The device of claim 10, wherein the read bias arrangement reads a data value on the second memory cell based on whether current flows from a source line of the second memory cell to the bit line coupled to the second memory cell.

20. A method of manufacturing a memory device, comprising:

providing a plurality of memory cells including a memory cell selected for programming;

providing a plurality of conductive lines coupled to the memory cells, the plurality of conductive lines including a first conductive line and a second conductive line; and

providing a control circuit applying, during a same period of programming the memory cell selected for programming, a first plurality of pulses to the first conductive line and a second plurality of pulses to the second conductive line during a same period, wherein the first plurality of pulses includes multiple pulses having different magnitudes, and the second plurality of pulses includes multiple pulses having different magnitudes.

21. A page buffer circuit, comprising:

a differential sense amplifier including a memory element with a previously sensed logic state; and

a page buffer logic circuit coupled to the memory element of the differential sense amplifier.

22. The circuit of claim 21, wherein:

the differential sense amplifier senses the logic state of memory cells having one of at least a low threshold voltage state and a high threshold voltage state, and

the page buffer logic circuit receives as input the previously sensed logic state, wherein responsive to the previously sensed logic state corresponding to the low threshold voltage state, the page buffer logic circuit allows a read operation to proceed on a memory cell without discharging a bit line coupled to the memory cell.