SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY

• US 20120281486A1
• Filed: 07/17/2012
• Published: 11/08/2012
• Est. Priority Date: 08/18/2008
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Rao, Shetti Shanmukheshwara, Goel, Ankur
• Granted Patent: US 8,699,281 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.

Claims

1. A semiconductor device comprising:

a pair of first data lines transferring complementary signals;

a second data line;

a first circuit coupled with the pair of first data lines to generate a control signal from the complementary signals;

a second circuit driving the second data line from a first potential level to a second potential level in response to the control signal; and

a third circuit driving the second data line from the first potential level to the second potential level in parallel to the second circuit in response to a potential level of the second data line exceeding a prescribed value.

2. The device as claimed in claim 1, further comprising a memory cell, wherein the complementary signals transmitted by the pair of first data lines is read out from the memory cell.

3. The device as claimed in claim 2, further comprising a sense amplifier amplifying the complementary signals on the pair of first data lines.

4. The device as claimed in claim 1, further comprising a fourth circuit coupled to the second data line to amplify the potential level of the second data line.

5. The device as claimed in claim 4, wherein the fourth circuit is connected to an end of the second data line, and the third circuit is connected to the other end of the second data line.

6. The device as claimed in claim 4, wherein the fourth circuit comprises a latch circuit for latching the logic level transmitted through the second data line.

7. The device as claimed in claim 1, further comprising a fifth circuit operative to precharge the second data line to the first potential level.

8. The device as claimed in claim 1, wherein

the second circuit includes an MIS transistor;

and

the second circuit receives the control signal with a gate terminal of the MIS transistor.

9. The device as claimed in claim 8, wherein one of source and drain terminals of the MIS transistor is connected to the second data line.

10. The device as claimed in claim 8, wherein the MIS transistor comprises an n-channel MIS transistor.

11. A method comprising:

providing complementary signals onto a pair of first data lines;

generating a control signal from the complementary signals;

driving a second data line from a first potential level to a second potential level in response to the control signal; and

supplementing the driving the second data line from the first potential level to the second potential level in response to a potential level of the second data line exceeding a prescribed value.

12. The method as claimed in claim 11, further comprising reading, before the providing the complementary signals;

the complementary signals from a memory cell.

13. The method as claimed in claim 12, further comprising amplifying, before the generating the control signal, the complementary signals on the pair of first data lines.

14. The method as claimed in claim 11, further comprising amplifying the potential level of the second data line.

15. The method as claimed in claim 14, wherein the amplifying the potential level of the second data line is carried out at an end of the second data line, and the supplementing the driving is carried out at the other end of the second data line.

16. The method as claimed in claim 14, further comprising latching, after the amplifying the potential level of the second data line, the potential level of the second data line.

17. The method as claimed in claim 11, further comprising precharging, before the driving the second data line, the second data line to the first potential level.

18. The method as claimed in claim 11, wherein the driving the second data line comprises receiving the control signal with a gate terminal of an MIS transistor.

19. The method as claimed in claim 18, wherein one of source and drain terminals of the MIS transistor is connected to the second data line.

20. The method as claimed in claim 18, wherein the MIS transistor comprises an n-channel MIS transistor.