Pseudo-random Number Generation Based on Periodic Sampling of One or More Linear Feedback Shift Registers

• US 20120281827A1
• Filed: 07/18/2012
• Published: 11/08/2012
• Est. Priority Date: 08/15/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wan, Wade Keith, Chen, Sherman (Xuemin)
• Granted Patent: US 8,831,216 B2
• Time in Patent Office: Days
• US Class Current: 380/46
• CPC Class Codes: H04L 9/0668 producing a non-linear pseudorandom sequence

Abstract

Disclosed are various embodiments for generating pseudo-random numbers. One such embodiment is an apparatus comprising digital hardware configured to generate pseudo-random numbers. The apparatus uses a linear feedback shift register in which the correlation between successive pseudo-random numbers is reduced.

Claims

1. An apparatus comprising:

digital hardware configured to generate pseudo-random numbers using a linear feedback shift register in which the correlation between successive pseudo-random numbers is reduced.

2. The apparatus of claim 1, wherein said digital hardware comprises flip-flops and gates.

3. The apparatus of claim 1, wherein said digital hardware comprises at least one nonlinear operator electrically coupled to a tap from the linear feedback shift register.

4. An apparatus comprising:

a linear feedback shift register (LFSR) configured to produce a plurality of bits at each of a plurality of successive iterations; and

an output configured to periodically sample the plurality of bits produced by the LFSR using a specified sampling period rather than at each of the successive iterations.

5. The apparatus of claim 4, wherein the specified sampling period is equal to a number of the plurality of bits produced by the LFSR.

6. The apparatus of claim 4, wherein n is a number of the plurality of bits produced by the LFSR and the specified sampling period is equal to 2n−

1.

7. The apparatus of claim 4, wherein the plurality of bits generated by the LFSR corresponds to a maximal length sequence.

8. The apparatus of claim 7, wherein n is a number of the plurality of bits produced by the LFSR and the maximal length sequence has outputs characterized by periodicity 2n−

1.

9. An apparatus comprising:

a linear feedback shift register (LFSR) configured to output a first plurality of bits; and

a nonlinear operator configured to output a second plurality of bits by performing a nonlinear operation on the first plurality of bits from the LFSR and an operand having a value specific to the LFSR.

10. The apparatus of claim 9, wherein the nonlinear operator comprises an XOR operator.

11. The apparatus of claim 9, wherein the operand comprises a unique bit sequence associated with the LFSR.

12. The apparatus of claim 9, wherein the plurality of bits generated by the LFSR corresponds to a maximal length sequence.