Super-Endurance Solid-State Drive with Endurance Translation Layer (ETL) and Diversion of Temp Files for Reduced Flash Wear

• US 20120284587A1
• Filed: 07/02/2012
• Published: 11/08/2012
• Est. Priority Date: 06/18/2008
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Yu, Frank, Ma, Abraham C., Chen, Shimon
• Granted Patent: US 8,959,280 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Claims

1. A super-endurance flash drive comprising:

a host interface for receiving host reads and host writes from a host;

a dynamic-random-access memory (DRAM) buffer for storing data;

a flash memory for storing data that is retained when power is lost, the flash memory being block-erasable and page-writeable;

a controller for controlling access to the flash memory and to the DRAM buffer in response to host reads and host writes received by the host interface, the controller writing host data to the DRAM buffer;

an Endurance Translation Layer (ETL) implemented in the DRAM buffer and controlled by the controller that uses the ETL to provide temporary storage to reduce flash wear;

a data write cache stored in the DRAM buffer and managed by the controller, wherein the controller manages non-temporary data;

a Redundant Array of Individual Disks (RAID) structure of data distribution in the DRAM buffer for writing new data across several channels of the flash memory, the RAID structure managed by the controller; and

a backup power supply for powering the DRAM buffer and the flash memory and the controller when power is lost, the backup power supply having a sufficient capacity for the controller to copy target data in the ETL to the flash memory according to a policy.

2. The super-endurance flash drive of claim 1 wherein the ETL implemented in the DRAM buffer comprises:

a page mapping table stored in the DRAM buffer and accessed by the controller, the page mapping table having entries selected by a logical address from the host;

a plurality of sub-sector mapping tables stored in the DRAM buffer and accessed by the controller, each sub-sector mapping table comprising a plurality of sector entries selected by a sector number within a page;

wherein a sector entry comprises;

a partial-sector bit that indicates when the entry is a full-sector entry for a full sector of data for the host and when the entry is a partial-sector entry for a partial sector of data from the host;

a page pointer that points to a page location in the DRAM buffer that stores the full sector of data or the partial sector of data;

when the entry is a full-sector entry, a sector identifier that identifies a sector within the page location;

when the entry is a partial-sector entry, a byte offset that identifies a starting byte location within the page location, and a length that indicates a length of the partial sector of data;

wherein full-sector entries and partial-sector entries are stored in the plurality of sub-sector mapping tables;

a data in buffer stored in the DRAM buffer and accessed by the controller; and

wherein each page of the stripe-ready unit includes full page data or grouped partial page data;

wherein the controller allows host write data to be stored in the data write cache, then a stripe-ready unit be written to the flash memory according to a policy.

3. The super-endurance flash drive of claim 2 wherein an entry in the mapping table comprises:

data-type bits that indicate a type of data stored for the logical address that selected the entry;

a pointer that points to a location in the DRAM buffer when a full page of host data is stored in the DRAM buffer, or points to a location in the flash memory when the full page of host data is stored in the flash memory, wherein the pointer points to a location in the DRAM buffer that stores a sub-sector mapping table in the plurality of sub-sector mapping tables when the host data is a partial page of data;

wherein the data-type bits indicate a data type that is selected from the group consisting of;

a File Allocation Table (FAT) entry;

a File Descriptor Block (FDB) entry;

a paging file created by a memory manager on the host that swaps data from a main memory on the host to the super-endurance flash drive;

a temporary file identified by a file extension in a FAT entry that indicates a temporary file created by a program executing on the host, the temporary file being deletable upon power off/loss; and

a user file that stores user or application data for a user of the host;

wherein the controller allows user files to be copied to the flash memory but prevents temporary files from being written to the flash memory,

whereby flash wear is reduced by preventing temporary files from being written to the flash memory.

4. The super-endurance flash drive of claim 1 wherein the ETL implemented in the DRAM buffer further comprises:

a bad block manager, activated when a block in the flash memory is erased to generate an erased block;

count means for counting a number of un-erased bits in a page in the erased block;

when the number of un-erased bits exceeds a lower threshold and does not exceed a higher threshold, marking the page as a protected page and increasing a number of error-correction code (ECC) bits stored for the protected page;

page marking means, activated when the number of un-erased bits exceeds the higher threshold, for marking the page as a bad page and not storing host data in the bad page;

repeat means for repeating the count means and the page marking means for all pages in the erased block;

bad page count means for counting a number of bad pages in the erased block;

block marking means, activated when the erased block has a number of bad pages that exceeds a block threshold, for marking the erased block as a bad block and not storing host data in any pages in the bad block.

5. The super-endurance flash drive of claim 1 wherein the ETL implemented in the DRAM buffer further comprises:

a data-in buffer stored in the DRAM buffer and accessed by the controller;

an in-line compression circuit that includes means for compressing the host writes, means for adding a header to compressed data, and means for updating a compressed mapping table;

wherein the controller further comprises an adaptive compress algorithm that selects an adequate algorithm to compress write data based on a type of data set;

whereby a size of write data is reduced, resulting in fewer writes to the flash memory to prolong flash endurance.

6. The super-endurance flash drive of claim 1 wherein the ETL implemented in the DRAM buffer further comprises;

a S.M.A.R.T. function that collects health information for a flash device,

wherein a warranty of the flash device is based on a number of years a customer purchased or is based on a total host write number of the flash drive.

7. An Endurance Translation Layer (ETL) method to increase endurance of a flash memory that has a low specified erase-cycle lifetime comprising:

controlling access to the flash memory and to a dynamic-random-access memory (DRAM) buffer in response to host reads and host writes received by a host interface, using a controller to write host data to the DRAM buffer;

creating an ETL in the DRAM buffer that is controlled by the controller and using the ETL to provide temporary storage to reduce flash wear;

distributing data in the DRAM buffer to form a Redundant Array of Individual Disks (RAID) structure of data distribution in the DRAM buffer for writing new data across several channels of the flash memory, the RAID structure managed by the controller;

searching a mapping table for a matching entry for the logical address from a standard host write;

reading data-type bits and a pointer from the matching entry;

identifying a data-type to be a non-temporary data-type;

wherein the controller manages non-temporary data.

8. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

using the controller to manage a data write cache stored in the DRAM buffer;

writing a full page of data stored in the ETL in the DRAM buffer that is pointed to by the pointer from the matching entry;

when the data from a host is for a partial page in the flash memory;

creating or locating a sub-sector mapping table that is pointed to by the pointer in the matching entry in the mapping table;

for each full sector of data from the host, updating an entry in the sub-sector mapping table to indicate a full-sector type and a pointer to the full sector of data that is stored into the DRAM buffer;

for a partial sector of data from the host, updating an entry in the sub-sector mapping table to indicate a partial-sector type and a pointer to a grouping page that stores partial sectors, and a length and a starting byte offset of the partial sector,

whereby the sub-sector mapping table has entries for full sectors and for the partial sector;

wherein each page of the stripe-ready unit includes full page data or grouped partial page data;

wherein the controller allows host write data to be stored in the data write cache, then the stripe-ready unit is written to the flash memory according to a policy.

9. The Endurance Translation Layer (ETL) method of claim 7 wherein the ETL implemented in the DRAM buffer further comprises:

controlling various functions using a packed manager;

managing a data write cache stored in the DRAM buffer;

writing a first write data from the host and a header to a beginning of the data write cache;

writing a new write data from the host and a header next to a previous data in the data write cache;

wherein when an updated write data is received from the host and an old data is in the data write cache, the controller discarding the old data and its header and moving a dirty data behind the old data and then appending the updated write data and its header;

wherein when the dirty data has a size of more than a stripe-ready unit and the data write cache is full, the controller writing the stripe-ready unit to the flash memory.

10. The Endurance Translation Layer (ETL) method of claim 7 wherein the ETL implemented in the DRAM buffer further comprises:

using the controller to manage a data write cache stored in the DRAM buffer;

receiving from a host an initial host write;

assigning data-type bits indicating a FAT type when the logical address from the host is within a File Allocation Table (FAT) range of addresses specified by a formatting operation for storing FAT entries;

assigning data-type bits indicating a FDB type when the logical address from the host is within a File Descriptor Block (FDB) range of addresses specified by an operating system for storing FDB entries;

assigning data-type bits indicating a user-file type when the data-type bits are not otherwise assigned;

writing the data-type bits assigned to the initial host write to a new entry in a mapping table having a pointer;

writing initial host data received from the host with the initial host write to a location in the ETL in the DRAM buffer pointed to by the pointer;

moving data stored in the DRAM buffer to the flash memory for stored data having data-type bits indicating the user-file type;

when power off/loss occurs, moving data stored in the ETL in the DRAM buffer to the flash memory for data having data-type bits indicating the FAT or FDB types, whereby flash wear is reduced to the flash memory.

11. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

creating a data write cache area in the DRAM buffer;

recording an access frequency for each Logical-Block Address (LBA);

wherein when the access frequency is larger than a predefined value, the LBA is categorized as a Frequent Accessed (FA), otherwise the LBA is categorized as a Non-Frequent Accessed (NFA);

when the accessed LBA is categorized as a FA, storing data in a FA cache area;

when the accessed LBA is categorized as a NFA, storing data in a NFA cache area;

wherein the NFA cache area has a higher priority to be written to the flash memory and to be overwritten by other FA or NFA LBA accesses.

12. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

using the controller to manage a data write cache stored in the DRAM buffer;

using the controller to manage incoming LBA addresses from a host;

checking at power up for misalignment between a file system address and a flash memory page to determine the offset needed for alignment;

adding an offset to an incoming logical block address to align the incoming logical block address to the flash memory page.

13. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

using the controller to manage a data write cache stored in the DRAM buffer;

operating an in-line compression circuit and compressing the host writes, for adding a header to compressed data, and updating a compressed mapping table;

wherein the controller further comprises various compress algorithms;

selecting an adequate algorithm to compress write data based on type of data set;

when a data set has an identical data set existing, using the compressed mapping table and pointing to the same compressed data set;

when a data set has a similar data set existing, using the compressed mapping table and pointing to the same compressed data plus using a pointer to point to the delta data;

when a data set has no similar data set existing, moving the compressed data to the DRAM buffer and updating a pointer in the compressed mapping table;

when a data size is not reduced after compression, retaining the original data;

whereby a size of write data is reduced, resulting in fewer writes to the flash memory to prolong flash endurance.

14. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

using the controller to manage a data read cache stored in the DRAM buffer;

means for receiving from a host a read request having a Logical Block Address (LBA);

means for reading data from the flash memory and providing the data to the host when no read error is detected;

first means, activated when a read error is detected, for performing an error-correction code (ECC) check to generate a number of error bits;

second means, activated when the number of error bits is below a first threshold, for correcting the error bits and for providing corrected data to the host using a first level of error correction; and

third means, activated when the number of error bits is above the first threshold and below a second threshold, for correcting the error bits by using a first level of error correction and for providing corrected data to the host, and for generating a software error correction code if not previously generated;

fourth means, activated when the number of error bits is above the second threshold and correctable by the ECC, for correcting the error bits by using a first level of error correction and for providing corrected data to the host, and for generating a software error correction code if not previously generated;

fifth means, activated when the number of error bits is above a first correction limit of the first level of error correction, for correcting the error bits by using software error correction code previously generated and for providing corrected data to the host;

sixth means, activated when the number of error bits is above the first correction limit of the first level of error correction and cannot be corrected by the software error correction code, for abandoning a striping data, for reconstructing the striping data by using parity striping data and other striping data in a striping group and for providing corrected data to the host; and

seventh means, activated when the number of error bits is above the first correction limit of the first level of error correction, and cannot be corrected by the software error correction code, and striping parity data is not available or cannot be used, for executing a reference voltage shift routine and for providing corrected data to the host.

15. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

using the controller to manage a data read cache stored in the DRAM buffer;

means for receiving from a host a read request having a Logical Block Address (LBA);

means for reading data from the flash memory and providing the data to the host when no read error is detected;

first means, activated when a read error is detected, for performing an error-correction code (ECC) check to generate a number of error bits;

second means, activated when the number of error bits is below a threshold, for correcting the error bits and for providing corrected data to the host using a first level of error correction;

third means, activated when the number of error bits is above the threshold and correctable by the ECC, for correcting the error bits by using a first level of error correction and for providing corrected data to the host, for relocating an old physical block of flash data to a new physical block location and for marking the old physical block as obsolete;

fourth means, activated when the number of error bits is above the first correction limit of the first level of error correction, for abandoning a striping data, for reconstructing the striping data by using parity striping data and other striping data in a striping group and for providing corrected data to the host, and for relocating an old physical block of flash data to a new physical block location and for marking the old physical block as obsolete; and

fifth means, activated when the number of error bits is above the first correction limit of the first level of error correction, and striping parity data is not available or cannot be used, for executing a reference voltage shift routine and for providing corrected data to the host.

16. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

using the controller to manage a data read cache stored in the DRAM buffer;

shift means, activated when a number of error bits is above a first correction limit of a first level of error correction, for shifting reference voltage levels by;

writing various register values to flash memory chip registers to adjust reference voltage levels for reading data within a flash memory chip;

wherein resulting reference voltage levels are higher or lower than a default reference voltage level;

reading data within the flash memory chip using adjusted reference voltages;

when read data is successful read using an adjusted reference voltage level and the first level of error correction, sending the corrected data to the host, and storing the adjusted voltage reference level for future use;

when read data is unsuccessful read using an adjusted reference voltage level and the first level of error correction, using a software error correction code previously generated and providing corrected data to the host, and storing the adjusted voltage reference level for future use;

when read data fails when using an adjusted reference voltage level, the first level error correction, and software error correction code previously generated, calculating a new adjusted reference voltage and using the new adjusted reference voltage level in a new iteration; and

when all predefined reference voltage levels have failed, reporting a fatal error without sending corrected data;

whereby reference voltage levels are adjusted when the number of error bits is above the first correction limit of the first level of error correction to prolong flash endurance.

17. The Endurance Translation Layer (ETL) method of claim 7 further comprising:

when an erased block in a flash memory has been erased, increasing an erase count in an erase count table for the erased block;

reading a page status table for the erased block, the page status table having a plurality of page entries, each page entry storing a status for a page in the erased block, the status including an indication of a bad page or of a good page;

for each page in the erased block, reading the page entry for the page from the page status table;

when the page status from the page status table is bad, processing a next page;

when the page status from the page status table is good, counting a number of un-erased bits in the page;

when the number of un-erased bits exceeds a first threshold, changing the page status to indicate a bad page in the page entry and increasing a bad page count;

when the number of un-erased bits is between a first threshold and a second threshold, and the page status from the page status table indicates that error-correction code (ECC) protection is needed, processing a next page;

when the number of un-erased bits is between a first threshold and a second threshold, and the page status from the page status table indicates that ECC protection is not needed, changing the page status in the page entry to indicate that ECC protection is needed and increasing an ECC protection page count;

when the bad page count for the erased block exceeds a third threshold, indicating that the erased block is a bad block and not writing new data to the erased block,

whereby bad erased blocks are identified by counting bad pages within the erased block and allowing bad pages to exist in a good block to prolong flash endurance.

18. An Endurance Translation Layer (ETL) method to increase endurance of a flash memory that has a low specified erase-cycle lifetime comprising:

creating an ETL in a dynamic-random-access memory (DRAM) buffer that is controlled by a controller and using the ETL to provide temporary storage to reduce flash wear;

creating a spare/swap area in the DRAM buffer;

operating a controller to use the spare/swap area in the DRAM buffer to merge valid data in a flash memory with new data to generate combined data; and

writing the combined data to the flash memory;

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory.

19. The Endurance Translation Layer (ETL) method of claim 18 further comprising:

providing wear-leveling control to flash blocks in the flash memory;

when the controller needs a flash block to write data to through a spare/swap area of the DRAM buffer, checking a block status/erase count table, and selecting a lowest erase count flash block from a list of blocks with an empty block status;

wherein a highest erase count flash block is not selected.

20. The Endurance Translation Layer (ETL) method of claim 18 further comprising:

providing wear-leveling control to flash blocks in the flash memory;

when a device is idle and a maximum erase count has reached a predetermined threshold, selecting a group of targeted used blocks with lowest erase counts and an equal number of targeted empty blocks with highest erase counts using a block status/erase count table, copying data from a lowest erase count flash block to a highest erase count flash block through a spare/swap area of the DRAM buffer, and erasing the lowest erase count flash block;

 

recycling the lowest erase count flash block;

 

minimizing a delta of an erase count of each block.

21. The Endurance Translation Layer (ETL) method of claim 18 further comprising:

creating a page status table in the DRAM buffer;

operating the controller to use the page status table in the DRAM buffer to record the status of each flash page;

when a flash block is erased, setting the page status of each page in the flash block to an empty page;

when a page is written, changing the page status to a used page;

when the host data writes to a same Logical Page Address, writing data to a new flash page and setting the page status for an old page to a deleted/trimmed page;

when a trim command is received from the host, setting a corresponding page status to a deleted/trimmed page;

when the page is identified as a bad page, setting the page status to a bad page;

during a garbage collection process, not moving pages indicated as deleted/trimmed pages to a new flash block;

creating a spare/swap area in the DRAM buffer;

operating the controller to use the spare/swap area in the DRAM buffer to merge valid data in flash memory and new data to generate combined data;

wherein the page status of each page in a targeted block is examined from page status table;

wherein valid data page has the page status indicating as a used page;

the page status not indicating as a bad page, an empty page, or a trimmed page;

writing the combined data to the flash memory;

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory.