PROTECTION OF A NON-VOLATILE MEMORY BY CHANGE OF INSTRUCTIONS

• US 20120284808A1
• Filed: 04/27/2012
• Published: 11/08/2012
• Est. Priority Date: 05/04/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Teglia, Yannick
• Granted Patent: US 9,165,165 B2
• Time in Patent Office: Days
• US Class Current: 726/34
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 21/561 Virus type analysis
• CPC Class Codes: G06F 21/566 Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities
• CPC Class Codes: G06F 21/6218 to a system of files or objects, e.g. local or distributed file system or database
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system

Abstract

A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.

Claims

1. A method for protecting a volatile memory against a virus, wherein:

rights of writing, reading, or execution are assigned to certain areas of the memory; and

a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.

2. The method of claim 1, wherein said list is stored at the same address as the concerned area.

3. The method of claim 1, wherein said list is stored in a table separate from the concerned area.

4. The method of claim 1, wherein the volatile memory is a RAM.

5. The method of claim 1, wherein the volatile memory is a stack associated with a processing unit.

6. The method of claim 1, wherein a second list of opcodes for which the access to the areas is authorized or forbidden is associated with each of these areas.

7. An electronic circuit capable of implementing the method of claim 1.