APPARATUS AND METHODS FOR BIASING POWER AMPLIFIERS

• US 20120286873A1
• Filed: 05/10/2012
• Published: 11/15/2012
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Li, Ping, DiCarlo, Paul T.
• Granted Patent: US 8,717,101 B2
• Time in Patent Office: Days
• US Class Current: 330/285
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/213 in integrated circuits
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03G 3/007 Control dependent on the supply voltage
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/3827 Portable transceivers

Abstract

Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled.

Claims

1. A power amplifier system comprising:

a power amplifier configured to amplify a radio frequency (RF) signal; and

a bias block for biasing the power amplifier, the bias block including a time-dependent signal generator configured to shape an enable signal of the power amplifier to generate a control current, a current amplifier configured to amplify the control current to generate a correction current, and a primary biasing circuit configured to generate a bias current for the power amplifier based at least partly on the correction current, the bias current configured to correct for a variation in gain of the power amplifier when the power amplifier is enabled.

2. The power amplifier system of claim 1 wherein the time-dependent signal generator includes a resistor-capacitor (RC) network.

3. The power amplifier system of claim 2 wherein the RC network includes a first resistor and a first capacitor electrically connected in series between the current amplifier and an input of the bias circuit configured to receive the enable signal.

4. The power amplifier system of claim 3 wherein the RC network further includes a second resistor having a first end electrically connected to the input of the current mirror and a second end electrically connected to the input of the bias circuit configured to receive the enable signal.

5. The power amplifier system of claim 4 wherein the second resistor has a resistance ranging between about 10 kΩ

and about 100 kΩ

.

6. The power amplifier system of claim 3 wherein the first capacitor has a capacitance ranging between about 10 pF and about 100 pF.

7. The power amplifier system of claim 6 wherein the first resistor has a resistance ranging between about 10 kΩ

and about 100 kΩ

.

8. The power amplifier system of claim 1 wherein the current amplifier includes a current mirror.

9. The power amplifier system of claim 8 wherein the current mirror includes a first bipolar transistor and a second bipolar transistor, the first bipolar transistor including an emitter electrically connected to an emitter of the second bipolar transistor and to a power low voltage, and a collector electrically connected to a base of the first bipolar transistor and to a base of the second bipolar transistor, the collector of the first bipolar transistor configured to receive at least a portion of the control current.

10. The power amplifier system of claim 9 wherein the current mirror further includes a resistor, a third bipolar transistor and a fourth bipolar transistor, the third bipolar transistor including an emitter electrically connected to an emitter of the fourth bipolar transistor and to the power low voltage, and a collector electrically connected to a first end of the resistor, to the collector of the second bipolar transistor, to a base of the third bipolar transistor, and to a base of the fourth bipolar transistor, the collector of the fourth bipolar transistor configured to generate the compensation current.

11. The power amplifier system of claim 10 wherein the resistor further includes a second end configured to receive the enable signal.

12. The power amplifier system of claim 1 further comprising a transceiver for providing the RF signal to the power amplifier.

13. The power amplifier system of claim 1 wherein the power amplifier includes a bipolar transistor having an emitter, a base and a collector, the base configured to receive the RF signal and the bias current.

14. The power amplifier system of claim 13 wherein the emitter is electrically connected to a power low voltage and the collector is configured to generate an amplified version of the RF signal.

15. The power amplifier system of claim 1 wherein the primary bias circuit includes a first resistor, a second resistor, a first bipolar transistor, and a second bipolar transistor, the first resistor including a first end electrically connected to the emitter of the first bipolar transistor at a node configured to receive the correction current, and a second end electrically connected to a first end of the second resistor at a node of the bias circuit configured to receive the enable signal, the second resistor including a second end electrically connected to a collector of the first bipolar transistor, a base of the first bipolar transistor, and to a base of the second bipolar transistor.

16. The power amplifier system of claim 15 wherein the second bipolar transistor includes a collector electrically connected to a battery voltage and an emitter configured to generate the bias current.

17. The power amplifier system of claim 16 wherein the primary bias circuit further includes a third bipolar transistor having an emitter electrically connected to the power low voltage and a base and a collector electrically connected to the emitter of the first bipolar transistor.

18. A method of biasing a power amplifier, the method comprising:

shaping an enable signal using a time-dependent signal generator to generate a control current;

amplifying the control current using a current amplifier to generate a correction current; and

generating a bias current for a power amplifier using a primary biasing circuit, the primary biasing circuit configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled.

19. The method of claim 18 wherein shaping the enable signal includes using a resistor-capacitor (RC) network of the time-dependent signal generator.

20. The method of claim 19 wherein the RC network includes a first resistor and a first capacitor electrically connected in series, the RC network configured to receive the enable signal and to generate the control current.

21. The method of claim 18 wherein amplifying the control current further includes amplifying the control current using a current mirror of the current amplifier.

22. The method of claim 18 wherein generating the bias current includes shaping the bias current so as to compensate for a gain variation of a heterojunction bipolar transistor (HBT).

23. A bias circuit for biasing a power amplifier, the bias circuit comprising:

a time-dependent signal generator configured to shape an enable signal of the power amplifier to generate a control current;

a current amplifier configured to amplify the control current to generate a correction current; and

a primary biasing block configured to generate a bias current for the power amplifier based at least partly on the correction current, the bias current configured to correct for a variation in gain of the power amplifier when the power amplifier is enabled.

24. The bias circuit of claim 23 wherein the time-dependent signal generator includes a resistor-capacitor (RC) network.

25. The bias circuit of claim 24 wherein the RC network includes a first resistor and a first capacitor electrically connected in series between the current amplifier and an input of the bias circuit configured to receive the enable signal.

26. The bias circuit of claim 23 wherein the current amplifier includes a current mirror.

27. The bias circuit of claim 23 wherein the primary bias block includes a first resistor, a second resistor, a first bipolar transistor, and a second bipolar transistor, the first resistor including a first end electrically connected to the emitter of the first bipolar transistor at a node configured to receive the correction current, and a second end electrically connected to a first end of the second resistor at a node of the bias circuit configured to receive the enable signal, the second resistor including a second end electrically connected to a collector of the first bipolar transistor, a base of the first bipolar transistor, and to a base of the second bipolar transistor.

28. The bias circuit of claim 27 wherein the second bipolar transistor includes a collector electrically connected to a battery voltage and an emitter configured to generate the bias current.