Interpolation-Based Digital Pre-Distortion Architecture

• US 20120286985A1
• Filed: 11/04/2011
• Published: 11/15/2012
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Procomm International Pte. Ltd. (Transpacific IP Group Limited)
• Original Assignee: Andrew LLC (CommScope Holding Company, Inc.)
• Inventors: Chandrasekaran, Rajiv, Vella-Coleiro, George P.
• Granted Patent: US 8,537,041 B2
• Time in Patent Office: Days
• US Class Current: 341/144
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages

Abstract

A non-linear amplifier is linearized using interpolation-based digital pre-distortion (DPD). In one embodiment, the digital input signal is interpolated to generate a higher-sample-rate signal that is then pre-distorted. The resulting higher-sample-rate pre-distorted signal is then decimated to generate a final pre-distorted digital signal that is converted into an analog pre-distorted signal by a digital-to-analog converter (DAC) before being applied to the amplifier. In a polyphase embodiment, different versions of the original input digital signal are generated, where each version is then pre-distorted using a different DPD module to generate a different intermediate pre-distorted digital signal. The intermediate pre-distorted signals are filtered and combined to generate the final pre-distorted digital signal. In both embodiments, better linearization (e.g., less aliasing) can be achieved without increasing the sample rate of the DAC and, in the polyphase embodiment, without increasing the processing speed of the DPD modules.

Claims

1. A signal-processing system that generates an analog output signal (e.g., y_amp (t)) from a digital input signal (e.g., x[n]), each digital signal in the system having a corresponding sample rate, the system comprising:

a digital pre-distortion (DPD) sub-system (e.g., 210) configured to perform DPD processing to generate a final pre-distorted digital signal (e.g., x_pd [n]) from the digital input signal, wherein the DPD sub-system interpolates the digital input signal based on an interpolation factor (e.g., L) greater than one prior to performing the DPD processing;

a digital-to-analog converter (DAC) (e.g., 220) configured to convert the final pre-distorted digital signal into an analog pre-distorted signal (e.g., x_pd (t)); and

an analog sub-system (e.g., 230) configured to generate the analog output signal from the analog pre-distorted signal.

2. The invention of claim 1, wherein the analog sub-system comprises a non-linear amplifier (e.g., 234) configured to generate the analog output signal.

3. The invention of claim 2, wherein the analog sub-system further comprises an upconverter (e.g., 232) configured to upconvert the analog pre-distorted signal prior to amplification by the non-linear amplifier.

4. The invention of claim 1, wherein the DPD sub-system comprises:

a pre-DPD processor (e.g., 212) configured to generate one or more versions (e.g., 213(i)) of the digital input signal, wherein the pre-DPD processor is configured to apply at least one interpolation filter (e.g., 404, 504) based on the interpolation factor to the digital input signal to generate at least one version of the digital input signal;

a digital pre-distorter (e.g., 214) configured to pre-distort the one or more versions of the digital input signal to generate one or more intermediate pre-distorted digital signals (e.g., 215(i)); and

a post-DPD processor (e.g., 216) configured to generate the final pre-distorted digital signal from the one or more intermediate pre-distorted digital signals.

5. The invention of claim 4, wherein the pre-DPD processor comprises an interpolator configured to generate a single interpolated version (e.g., 213(1)) of the digital input signal by interpolating the digital input signal based on the interpolation factor, wherein the sample rate of the single interpolated version of the digital input signal is equal to a product of (i) the interpolation factor and (ii) the sample rate (e.g., F_s) of the digital input signal.

6. The invention of claim 5, wherein the digital pre-distorter comprises a single DPD module that performs the DPD processing on the single interpolated version of the digital input signal to generate a single intermediate pre-distorted digital signal (e.g., 215(1)) having its sample rate equal to the sample rate of the single interpolated version of the digital input signal.

7. The invention of claim 6, wherein the post-DPD processor comprises a decimator configured to generate the final pre-distorted digital signal by decimating the intermediate pre-distorted digital signal based on a decimation factor (e.g., N).

8. The invention of claim 7, wherein the decimation factor is equal to the interpolation factor such that the sample rate of the final pre-distorted digital signal is equal to the sample rate of the digital input signal.

9. The invention of claim 7, wherein:

the interpolator comprises an upsampling module (e.g., 402) followed by an interpolation filter (e.g., 404); and

the decimator comprises a decimation filter (e.g., 406) followed by a downsampling module (e.g., 408).

10. The invention of claim 4, wherein:

the pre-DPD processor is configured to generate a plurality (e.g., M) of versions (e.g., 213(i)) of the digital input signal based on the interpolation factor;

the digital pre-distorter comprises a plurality (e.g., M) of DPD modules (e.g., 506(i)) configured to generate a plurality (e.g., M) of intermediate pre-distorted digital signals (e.g., 215(i)) from the plurality of versions of the digital input signal, each DPD module configured to perform DPD processing on a different version of the digital input signal to generate a corresponding intermediate pre-distorted digital signal; and

the post-DPD processor is configured to generate the final pre-distorted digital signal from the plurality of intermediate pre-distorted digital signals.

11. The invention of claim 10, wherein:

the sample rate of each version of the digital input signal is equal to the sample rate (e.g., F_s) of the digital input signal; and

the sample rate of each intermediate pre-distorted digital signal is equal to the sample rate of the digital input signal.

12. The invention of claim 11, wherein the sample rate of the final pre-distorted digital signal is equal to the sample rate of the digital input signal.

13. The invention of claim 10, wherein:

the interpolation factor is two;

the pre-DPD processor is configured to generate two versions (e.g., 213(1) and 213(2)) of the digital input signal based on the interpolation factor;

the digital pre-distorter comprises two DPD modules (e.g., 506(1) and 506(2)) configured to generate two intermediate pre-distorted digital signals (e.g., 215(1) and 215(2)) from two versions of the digital input signal; and

the post-DPD processor is configured to generate the final pre-distorted digital signal from the two intermediate pre-distorted digital signals.

14. The invention of claim 13, wherein:

the pre-DPD processor comprises;

a delay module (e.g., 502) configured to delay a first copy of the digital input signal to generate a first version (e.g., 213(1)) of the digital input signal; and

a pre-DPD filter (e.g., 504) configured to filter a second copy of the digital input signal to generate a second version (e.g., 213(2)) of the digital input signal, wherein;

the second version of the digital input signal comprises only interpolated values of an interpolated digital signal (e.g., 213(1) of FIG. 4) that would be generated by applying a 2×

interpolation filter (e.g., 404) to a zero-stuffed version (e.g., 403) of the digital input signal; and

the pre-DPD filter comprises only the odd-numbered coefficients of the 2×

interpolation filter;

the two DPD modules of the digital pre-distorter perform the same DPD processing on the first and second versions of the digital input signal to generate first and second intermediate pre-distorted digital signals (e.g., 215(1) and 215(2)); and

the post-DPD processor comprises;

a first post-DPD filter (e.g., 508) configured to filter the first intermediate pre-distorted digital signal to generate a first filtered digital signal (e.g., 511(1)), wherein the coefficients of the first post-DPD filter correspond to the even-numbered coefficients of a 2×

decimation filter (e.g., 406);

a second post-DPD filter (e.g., 510) configured to filter the second intermediate pre-distorted digital signal to generate a second filtered digital signal (e.g., 511(2)), wherein the coefficients of the second post-DPD filter correspond to the odd-numbered coefficients of the 2×

decimation filter; and

a summation node (e.g., 512) configured to combine the first and second filtered digital signals to generate the final pre-distorted digital signal.

15. The invention of claim 14, wherein the sample rate of each of the first and second versions of the digital input signal, first and second intermediate pre-distorted digital signals, the first and second filtered pre-distorted digital signals, and the final pre-distorted digital signal is equal to the sample rate (e.g., F_s) of the digital input signal.