INPUT SIGNAL CORRECTION ARCHITECTURE

• US 20120287077A1
• Filed: 05/13/2011
• Published: 11/15/2012
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Pant, Vivek, Shahparnia, Shahrooz, Schwartz, Adam
• Granted Patent: US 9,857,921 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A capacitive input device processing system comprises input signal correction circuitry. The input signal correction circuitry includes an amplifier, a correction signal generator, and a charge collection mechanism. The amplifier is configured to receive a combination signal. The combination signal comprises a resulting signal from a sensor element and a correction charge. The correction signal generator is configured to generate a correction signal. The charge collection mechanism is configured to accumulate the correction charge from the correction signal.

Claims

1. A capacitive input device processing system comprising:

input signal correction circuitry comprising;

an amplifier configured to receive a combination signal, the combination signal comprising a resulting signal from a sensor element and a correction charge;

a correction signal generator configured to generate a correction signal; and

a charge collection mechanism configured to accumulate said correction charge from said correction signal.

2. The capacitive input device processing system of claim 1, further comprising:

a control module configured to operate said correction signal generator.

3. The capacitive input device processing system of claim 2, wherein said control module is further configured to adjust a charge collection value of said charge collection mechanism.

4. The capacitive input device processing system of claim 3, wherein said control module adjusts said charge collection value based on an output signal of said amplifier.

5. The capacitive input device processing system of claim 3, wherein said control module adjusts said charge collection value in response to said input device operating in a noise detection mode.

6. The capacitive input device processing system of claim 2, wherein said amplifier is an integrating amplifier configured with a feedback capacitor and wherein said control module is further configured to modify a gain of said integrating amplifier by adjusting a capacitance value of said feedback capacitor.

7. The capacitive input device processing system of claim 2, wherein said control module is further configured to adjust at least one of a phase and an amplitude of said correction signal.

8. The capacitive input device processing system of claim 2, wherein said control module is further configured to adjust at least one of an aspect of said correction signal and a charge collection value of said charge collection mechanism, such that said correction charge modifies an amplitude of said combination signal.

9. The capacitive input device processing system of claim 1, wherein said charge collection mechanism is configured to combine said correction charge with said resulting signal to form said combination signal prior to an input of said amplifier.

10. A capacitive input device comprising:

a sensor element configured to convey a resulting signal indicative of input in a sensing region,

an amplifier configured to receive a combination signal comprising said resulting signal and a correction charge, said amplifier further configured to provide an output signal corresponding to said resulting signal and said correction charge; and

a control module configured to analyze said output signal and change a gain of said amplifier based on a parameter of said output signal.

11. The capacitive input device of claim 10, further comprising:

a correction signal generator configured to generate a correction signal; and

a charge collection mechanism configured to accumulate said correction signal into said correction charge.

12. The capacitive input device of claim 11, wherein said control module is further configured to adjust a charge collection value of said charge collection mechanism based on said output signal.

13. The capacitive input device of claim 11, wherein said control module is further configured to adjust said charge collection value in response to said input device operating in a noise detection mode.

14. The capacitive input device of claim 11, wherein said control module is further configured to adjust at least one of a phase and an amplitude of said correction signal.

15. The capacitive input device of claim 11, wherein said control module is further configured to adjust at least one of an aspect of said correction signal and a charge collection value of said charge collection mechanism, such that said correction charge modifies an amplitude of said combination signal.

16. The capacitive input device of claim 11, wherein said charge collection mechanism is configured to combine said correction charge with said resulting signal to form said combination signal at a location prior to an input of said combination signal at said amplifier.

17. A method of operating a capacitive input device, wherein the capacitive input device comprises input signal processing circuitry, said method comprising:

amplifying a first resulting signal conveyed by a sensor element to an input of said input signal processing circuitry, wherein said first resulting signal is amplified into an output signal by said input signal processing circuitry;

analyzing said output signal;

operating a correction signal generator to produce a correction signal;

accumulating a correction charge from said correction signal; and

providing said correction charge to said input of said input signal processing circuitry such that said correction charge is combined with a second resulting signal.

18. The method as recited in claim 17, further comprising:

adjusting a gain of said input signal processing circuitry based on a parameter of said output signal.

19. The method as recited in claim 17, further comprising:

adjusting at least one aspect of said correction signal and a charge collection value of a charge collection mechanism which accumulates said correction signal from said correction charge, such that said correction charge adjusts a Direct Current (DC) baseline of said second resulting signal.

20. The method as recited in claim 17, wherein said operating a correction signal generator to produce a correction signal comprises:

selecting an amplitude of said correction signal based on said analysis of said output signal.