Display Interface Circuit
First Claim
1. A display interface circuit for coordinating a processor and a display panel of a mobile device, the interface circuit comprising:
- an analog circuit module, comprising a physical layer circuit, for receiving and modulating an original data signal and an original clock signal provided by the processor, and respectively generating a data signal and a clock signal accordingly, to conform to an industry specification;
a frame buffer, for storing the data signal according to an access signal and the clock signal, and outputting the data signal to the display panel according to a command signal; and
a digital circuit module, comprising;
a display serial interface (DSI), coupled to the physical layer circuit, for transmitting the data signal and the clock signal through packetization;
a memory controller, coupled between the display serial interface and the frame buffer, for generating the access signal according to the data signal and the clock signal;
a configuration register, for generating the command signal according to an asynchronous clock signal and the data signal; and
an asynchronous delay circuit, coupled between the display serial interface and the configuration register, for adjusting a clock latency taken for the clock signal to be sent to the configuration register, to generate the asynchronous clock signal.
1 Assignment
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Accused Products
Abstract
A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal.
18 Citations
7 Claims
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1. A display interface circuit for coordinating a processor and a display panel of a mobile device, the interface circuit comprising:
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an analog circuit module, comprising a physical layer circuit, for receiving and modulating an original data signal and an original clock signal provided by the processor, and respectively generating a data signal and a clock signal accordingly, to conform to an industry specification; a frame buffer, for storing the data signal according to an access signal and the clock signal, and outputting the data signal to the display panel according to a command signal; and a digital circuit module, comprising; a display serial interface (DSI), coupled to the physical layer circuit, for transmitting the data signal and the clock signal through packetization; a memory controller, coupled between the display serial interface and the frame buffer, for generating the access signal according to the data signal and the clock signal; a configuration register, for generating the command signal according to an asynchronous clock signal and the data signal; and an asynchronous delay circuit, coupled between the display serial interface and the configuration register, for adjusting a clock latency taken for the clock signal to be sent to the configuration register, to generate the asynchronous clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification