SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SEMICONDUCTOR DEVICE

• US 20120287693A1
• Filed: 05/09/2012
• Published: 11/15/2012
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Furutani, Kazuma
• Granted Patent: US 8,897,049 B2
• Time in Patent Office: Days
• US Class Current: 365/49.17
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence

Abstract

To provide a semiconductor device whose power can be turned off without the need for a peripheral circuit for data to escape temporarily and in which stored data is not lost even in an off state of the power of the device, and a memory device including the semiconductor device. In a holding circuit of the semiconductor device, a transistor that includes a semiconductor layer (at least a channel formation region) including an oxide semiconductor material with which small off-state current can be achieved is used. Further, the semiconductor device includes a switching element which enables a comparison circuit in which comparison between data stored in the holding circuit and reference data input from the outside does not need to be performed to become forcibly inactive.

Claims

1. A semiconductor device comprising:

a holding circuit comprising a first transistor and a capacitor electrically connected to the first transistor;

a comparison circuit comprising a first arithmetic circuit and a second arithmetic circuit electrically connected to the first arithmetic circuit; and

a switching element,

wherein the first transistor includes a first oxide semiconductor layer,

wherein the holding circuit is electrically connected to the first arithmetic circuit and the second arithmetic circuit,

wherein the switching element is electrically connected to the first arithmetic circuit and the second arithmetic circuit, and

wherein the first arithmetic circuit and the second arithmetic circuit are configured to change a potential of a output signal line electrically connected to the switching element.

2. The semiconductor device according to claim 1,

wherein the switching element is a transistor including a second oxide semiconductor layer.

3. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer comprises at least one of indium and zinc.

4. The semiconductor device according to claim 1,

wherein the first arithmetic circuit comprises a second transistor and a third transistor having a different channel conductivity type from the second transistor, and

wherein the second transistor is electrically connected to the third transistor.

5. The semiconductor device according to claim 1,

wherein the second arithmetic circuit comprises a fourth transistor having a different channel conductivity type from the second transistor and a fifth transistor having a different channel conductivity type from the fourth transistor, and

wherein the fourth transistor is electrically connected to the fifth transistor.

6. The semiconductor device according to claim 1,

wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the capacitor, a gate electrode of the third transistor, and a gate electrode of the fifth transistor.

7. The semiconductor device according to claim 1,

wherein a gate electrode of the second transistor and a gate electrode of the fourth transistor are electrically connected to an input signal line.

8. The semiconductor device according to claim 1,

wherein one of a source electrode and a drain electrode of the second transistor and one of a source electrode and a drain electrode of the fourth transistor are electrically connected to the switching element,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the third transistor, and

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the fifth transistor.

9. A memory device comprising the semiconductor device according to claim 1,

wherein a plurality of the semiconductor devices are arranged in a matrix.

10. The memory device according to claim 9 further comprising:

a detection circuit configured to detect a change in the potential of the output signal line in at least one of the plurality of the semiconductor devices,

wherein the detection circuit outputs a first signal when the change in the potential is detected by the detection circuit, and

wherein the detection circuit outputs a second signal which is different from the first signal when the change in the potential is not detected by the detection circuit.

11. A semiconductor device comprising:

a holding circuit comprising a first transistor and a capacitor electrically connected to the first transistor, wherein storage data is input to the capacitor;

a comparison circuit comprising a first arithmetic circuit and a second arithmetic circuit electrically connected to the first arithmetic circuit, wherein reference data is input to each of the first arithmetic circuit and the second arithmetic circuit so that the first arithmetic circuit and the second arithmetic circuit each compares the storage data with the reference data; and

a switching element,

wherein the first transistor includes a first oxide semiconductor layer,

wherein the holding circuit is electrically connected to the first arithmetic circuit and the second arithmetic circuit,

wherein the switching element is electrically connected to the first arithmetic circuit and the second arithmetic circuit, and

wherein the first arithmetic circuit and the second arithmetic circuit is configured to change a potential of a output signal line electrically connected to the switching element when at least one of the first arithmetic circuit and the second arithmetic circuit and the switching element are in a conductive state.

12. The semiconductor device according to claim 11,

wherein the switching element is a transistor including a second oxide semiconductor layer.

13. The semiconductor device according to claim 11,

wherein the first oxide semiconductor layer comprises at least one of indium and zinc.

14. The semiconductor device according to claim 11,

wherein the first arithmetic circuit comprises a second transistor and a third transistor having a different channel conductivity type from the second transistor, and

wherein the second transistor is electrically connected to the third transistor.

15. The semiconductor device according to claim 11,

wherein the second arithmetic circuit comprises a fourth transistor having a different channel conductivity type from the second transistor and a fifth transistor having a different channel conductivity type from the fourth transistor, and

wherein the fourth transistor is electrically connected to the fifth transistor.

16. The semiconductor device according to claim 11,

wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the capacitor, a gate electrode of the third transistor, and a gate electrode of the fifth transistor.

17. The semiconductor device according to claim 11,

wherein a gate electrode of the second transistor and a gate electrode of the fourth transistor are electrically connected to an input signal line.

18. The semiconductor device according to claim 11,

wherein one of a source electrode and a drain electrode of the second transistor and one of a source electrode and a drain electrode of the fourth transistor are electrically connected to the switching element,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the third transistor, and

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the fifth transistor.

19. A memory device comprising the semiconductor device according to claim 11,

wherein a plurality of the semiconductor devices are arranged in a matrix.

20. The memory device according to claim 19 further comprising:

a detection circuit configured to detect a change in the potential of the output signal line in at least one of the plurality of the semiconductor devices,

wherein the detection circuit outputs a first signal when the change in the potential is detected by the detection circuit, and

wherein the detection circuit outputs a second signal which is different from the first signal when the change in the potential is not detected by the detection circuit.

21. The semiconductor device according to claim 11,

wherein a third signal is output to the output signal line when at least one of the first arithmetic circuit and the second arithmetic circuit and the switching element are in a conductive state.