Method and system of complete mutual access of multiple-processors

• US 20120290763A1
• Filed: 06/04/2010
• Published: 11/15/2012
• Est. Priority Date: 12/29/2009
• Status: Abandoned Application

• Current Assignee: ZTE Corporation
• Original Assignee: ZTE Corporation
• Inventors: Li, Chuang
• Application Number:
  US13/519,593
• Publication Number:
  US 20120290763A1
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

The present disclosure discloses a method of complete mutual access of multiple-processors. The method comprises: a separate boot memory and a separate address mapping module are allocated for each processor; the processors perform the mutual access in the multiple-processors through the address mapping module after the processors are booted. The present disclosure also discloses a system for enabling complete mutual access of the multiple-processors. The method and the system creates the advantage of allowing complete mutual access of the multiple-processors, thereby sharing address space in the multiple-processors, sharing the peripheral controller and memory, improving expansibility and performance of the system.

Claims

1. A method of complete mutual access of multiple processors, comprising the following steps:

allocating a separate boot memory and a separate address mapping module for each processor; and

realizing the mutual access among the multiple processors through the address mapping module after any processor is booted.

2. The method according to claim 1, further comprising:

before the processor is booted, guiding each processor to be booted after powered on.

3. The method according to claim 2, further comprising:

mapping a head address of each processor to the boot memory corresponding to the processor through the address mapping module during boot initialization of the processor.

4. The method according to claim 1, further comprising:

setting a mailbox for sharing communication between each two processors.

5. The method according to claim 4, wherein realizing the mutual access among multiple processors comprises:

converting, by the address mapping module, a logic address sent out by a processor into a physical address identifiable by another processor so as to realize the mutual access among the processors.

12. The method according to claim 2, further comprising:

setting a mailbox for sharing communication between each two processors.

13. The method according to claim 3, further comprising:

setting a mailbox for sharing communication between each two processors.

14. The method according to claim 12, wherein realizing the mutual access among multiple processors comprises:

converting, by the address mapping module, a logic address sent out by a processor into a physical address identifiable by another processor so as to realize the mutual access among the processors.

15. The method according to claim 13, wherein realizing the mutual access among multiple processors comprises:

converting, by the address mapping module, a logic address sent out by a processor into a physical address identifiable by another processor so as to realize the mutual access among the processors.

6. A system of complete mutual access of multiple-processors, comprising:

a multi-processor module, one or more address mapping modules, an on-chip interconnection bus, and a memory module, wherein

the multi-processor module includes one or more processors for processing all data in the system;

the address mapping module is configured to convert a logic address sent out by a processor in the multi-processor module into a corresponding physical address identifiable by another processor;

the on-chip interconnection bus is configured to transmit data, data addresses and control signals; and

the memory module includes a main memory and one or more boot memories for storing application programs and data;

wherein each processor corresponds to one boot memory and one address mapping module.

7. The system according to claim 6, further comprising:

at least one mailbox and/or at least one peripheral controller, wherein

each mailbox is arranged between each two processors for sharing communication therebetween; and

the peripheral controller is configured to carry a peripheral device.

8. The system according to claim 6, further comprising:

a boot module and/or a Direct Memory Access (DMA) module, wherein

the boot module is configured to guide the boot of each processor; and

the DMA module is configured to transport data.

9. The system according to claim 8, wherein the on-chip interconnection bus includes at least one level of buses, wherein

a first-level bus is configured to connect the multi-processor module with the memory module;

and

a second-level bus or a subordinate level bus is configured to connect a superior bus with the peripheral controller and the mailbox.

10. The system according to claim 9, further comprising:

a bridge configured to connect two levels of buses.

11. The system according to claim 10, further comprising:

a bypass module configured to provide the processor with a communication path for directly accessing the second-level bus without passing through the first-level bus.

16. The system according to claim 7, further comprising:

a boot module and/or a Direct Memory Access (DMA) module, wherein

the boot module is configured to guide the boot of each processor; and

the DMA module is configured to transport data.

17. The system according to claim 16, wherein the on-chip interconnection bus includes at least one level of buses, wherein

a first-level bus is configured to connect the multi-processor module with the memory module;

and

a second-level bus or a subordinate level bus is configured to connect a superior bus with the peripheral controller and the mailbox.

18. The system according to claim 17, further comprising:

a bridge configured to connect two levels of buses.

19. The system according to claim 18, further comprising:

a bypass module configured to provide the processor with a communication path for directly accessing the second-level bus without passing through the first-level bus.