TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
First Claim
1. A method of reducing total power dissipation for logic cells, comprising:
- selecting a distribution of logic cells corresponding to at least one path;
computing a dynamic to static power ratio for each logic cell in the distribution of logic cells;
ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells;
swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells; and
verifying path timing for the reconfigured middle group of logic cells.
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Abstract
A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
4 Citations
19 Claims
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1. A method of reducing total power dissipation for logic cells, comprising:
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selecting a distribution of logic cells corresponding to at least one path; computing a dynamic to static power ratio for each logic cell in the distribution of logic cells; ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells; swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells; and verifying path timing for the reconfigured middle group of logic cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of reducing total power dissipation for groups of logic cells using Boolean equations, comprising:
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selecting a path; identifying at least one group of logic cells for analysis in the path; deriving Boolean equations for the at least one group of logic cells; listing possible logic cell implementations for each Boolean equation while maintaining original transistor values; verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement; computing a total power dissipation for the retained logic cells; and choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of reducing total power dissipation for logic cell sets, comprising:
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selecting a path; choosing a logic cell in the path; computing a starting total power for the logic cell; identifying logic cell implementations using different transistor values for logic cell swapping; verifying path timing for the logic cell implementations to generate timing-verified logic cells that achieve a timing requirement for the path; comparing an ending total power of the timing-verified logic cells with the starting total power of the logic cell; choosing one of the timing verified logic cells or the logic cell based on achieving a minimum total power for the path. - View Dependent Claims (16, 17, 18, 19)
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Specification