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TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT

  • US 20120290994A1
  • Filed: 05/09/2011
  • Published: 11/15/2012
  • Est. Priority Date: 05/09/2011
  • Status: Active Grant
First Claim
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1. A method of reducing total power dissipation for logic cells, comprising:

  • selecting a distribution of logic cells corresponding to at least one path;

    computing a dynamic to static power ratio for each logic cell in the distribution of logic cells;

    ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells;

    swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells; and

    verifying path timing for the reconfigured middle group of logic cells.

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