OXIDE SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING OXIDE SEMICONDUCTOR DEVICES, DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES

• US 20120292610A1
• Filed: 09/09/2011
• Published: 11/22/2012
• Est. Priority Date: 05/17/2011
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Wang, Seong-Min, Yoon, Joo-Sun, Kim, Ki-Hong, Ahn, Ki-Wan
• Application Number:
  US13/229,606
• Publication Number:
  US 20120292610A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1201 Manufacture or treatment

Abstract

An oxide semiconductor device includes a gate electrode on a substrate, a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode, a source electrode on a first portion of the gate insulation layer, a drain electrode on a second portion of the gate insulation layer, and an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure.

Claims

1. An oxide semiconductor device comprising:

a gate electrode on a substrate;

a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode;

a source electrode on a first portion of the gate insulation layer;

a drain electrode on a second portion of the gate insulation layer; and

an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure.

2. The oxide semiconductor device of claim 1, wherein each of the source electrode and the drain electrode comprises at least one material selected from the group consisting of a metal, an alloy, a metal nitride, a conductive metal oxide and a transparent conductive material.

3. The oxide semiconductor device of claim 1, wherein the active pattern comprises a semiconductor oxide including a binary compound (AB_x), a ternary compound (AB_xC_y) or a quaternary compound (AB_xC_yD_z).

4. The oxide semiconductor device of claim 3, wherein the semiconductor oxide comprises at least one material selected from the group consisting of indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr) and magnesium (Mg).

5. The oxide semiconductor device of claim 3, wherein the active pattern further comprises at least one material selected from the group consisting of lithium (Li), sodium (Na), manganese (Mn), nickel (Ni), palladium (Pd), copper (Cu), carbon (C), nitrogen (N), phosphorus (P), titanium (Ti), zirconium (Zr), vanadium (V), ruthenium (Ru), germanium (Ge), tin (Sn) and fluorine (F).

6. The oxide semiconductor device of claim 1, wherein the recess structure is formed by performing at least one of a plasma treatment or a cleaning treatment on the gate insulation layer.

7. The oxide semiconductor device of claim 1, wherein the recess structure has a sidewall having a first angle of inclination relative to the substrate, and each of the source electrode and the drain electrode has a sidewall, one of the sidewalls having a second angle of inclination with respect to the substrate.

8. The oxide semiconductor device of claim 7, wherein the second angle of inclination is greater than the first angle of inclination.

9. The oxide semiconductor device of claim 8, wherein a ratio between the first angle of inclination and the second angle of inclination is in a range from about 1.0:

0.5 to about 1.0;

9.0.

10. The oxide semiconductor device of claim 1, wherein a lower portion of the active pattern fills the recess structure and a central portion of the active pattern contacts the source electrode and the drain electrode.

11. The oxide semiconductor device of claim 10, wherein an inclined angle, relative to the substrate, of a sidewall of the central portion of the active pattern is greater than an inclined angle, relative to the substrate, of a sidewall of the lower portion of the active pattern.

12. The oxide semiconductor device of claim 11, wherein a ratio between the inclined angle of the sidewall of the lower portion and the inclined angle of the sidewall of the central portion is in a range from about 1.0:

0.5 to about 1.0;

9.0.

13. The oxide semiconductor device of claim 1, wherein the gate insulation layer has a level upper face.

14. The oxide semiconductor device of claim 13, wherein a ratio between a depth of the recess structure and a thickness of the gate insulation layer is in a range from about 1.0:

1.7 to about 1.0;

30.0.

15. The oxide semiconductor device of claim 1, wherein the gate insulation layer includes a stepped portion adjacent to the gate electrode.

16. The oxide semiconductor device of claim 15, wherein a ratio between a depth of the recess structure and a thickness of the gate insulation layer is in a range from about 1.0:

1.7 to about 1.0;

10.0.

17. The oxide semiconductor device of claim 15, wherein each of the source electrode and the drain electrode includes a stepped portion adjacent to the stepped portion of the gate insulation layer.

18. The oxide semiconductor device of claim 1, wherein the source electrode comprises a first electrode pattern and a second electrode pattern, and the drain electrode comprises a third electrode pattern and a fourth electrode pattern.

19. The oxide semiconductor device of claim 18, wherein each of the first electrode pattern and the third electrode pattern comprises at least one material selected from the group consisting of a metal, an alloy and a transparent conductive material, and each of the second electrode pattern and the fourth electrode pattern comprises one of a metal nitride and a nitride of a transparent conductive material.

20. A method of manufacturing an oxide semiconductor device, comprising:

forming a gate electrode on a substrate;

forming a gate insulation layer on the substrate to cover the gate electrode;

forming an electrode layer on the gate insulation layer;

forming a mask pattern on the electrode layer;

forming a source electrode and a drain electrode on the gate insulation layer by etching the electrode layer using the mask pattern;

forming a recess structure on the gate insulation layer and between the source electrode and the drain electrode; and

forming an active pattern on the gate insulation layer, the source electrode and the drain electrode.

21. The method of claim 20, wherein the recess structure is formed by performing at least one of a plasma treatment or a cleaning treatment.

22. The method of claim 21, wherein the plasma treatment is carried out using a plasma generated from at least one gas selected from the group consisting of a gas including sulfur fluoride (SE_x), a gas including chlorine fluoride (ClF_x), a gas including hydrogen chloride (HCl), a gas including boron chloride (BCl_x), a gas including hydrocarbon (C_xH_y), a gas including oxygen (O₂) and a gas including ozone (O₃).

23. The method of claim 21, wherein the cleaning treatment is performed by applying a solution for removing a metal compound.

24. The method of claim 23, wherein the solution for removing the metal compound includes at least one solution selected from the group consisting of a solution containing hydrogen fluoride (HF), a solution containing hydrogen chloride (HCl), a solution containing phosphoric acid (H₃PO₄), a solution containing potassium hydroxide (KOH), a solution containing hydrogen bromide (HBr) and a solution containing iodine bromide (IBr).

25. The method of claim 21, further comprising removing the mask pattern from the source electrode and the drain electrode after forming the recess structure.

26. The method of claim 20, wherein the forming the recess structure further comprises:

forming a preliminary recess structure on the gate insulation layer by performing a plasma treatment on the gate insulation layer between the source electrode and the drain electrode;

removing the mask pattern from the source electrode and the drain electrode; and

performing a cleaning treatment on the gate insulation layer having the preliminary recess structure.

27. The method of claim 20, wherein the forming the recess structure further comprises:

forming a preliminary recess structure on the gate insulation layer by performing a plasma treatment on the gate insulation layer between the source electrode and the drain electrode;

forming the recess structure on the gate insulation layer by performing a cleaning treatment on the gate insulation layer having the preliminary recess structure; and

removing the mask pattern from the source electrode and the drain electrode.

28. The method of claim 20, wherein the forming the electrode layer further comprises:

forming a first electrode film on the gate insulation layer; and

forming a second electrode film on the first electrode film.

29. The method of claim 28, wherein the forming the second electrode film includes nitriding the first electrode film.

30. The method of claim 29, wherein the forming the second electrode film includes one of:

thermally treating the first electrode film under an atmosphere containing nitrogen; and

treating the first electrode film with a plasma generated from a gas containing nitrogen.

31. The method of claim 28, wherein the forming the source electrode and the drain electrode further comprises partially etching the second electrode film and the first electrode film to form a first electrode pattern and a second electrode pattern on a first portion of the gate insulation layer and to form a third electrode pattern and a fourth electrode pattern on a second portion of the gate insulation layer.

32. The method of claim 28, wherein the forming the recess structure further comprises:

removing the mask pattern from the source electrode and the drain electrode; and

performing at least one of a plasma treatment or a cleaning treatment on the gate insulation layer between the source electrode and the drain electrode.

33. A display device comprising:

a substrate;

a gate electrode on the substrate;

a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode;

a source electrode on a first portion of the gate insulation layer;

a drain electrode on a second portion of the gate insulation layer;

an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure;

a first electrode electrically connected to the drain electrode;

a light emitting layer on the first electrode; and

a second electrode on the light emitting layer.

34. The display device of claim 33, wherein the recess structure has a sidewall having a first angle of inclination relative to the substrate, and each of the source electrode and the drain electrode has a sidewall, one of the sidewalls having a second angle of inclination with respect to the substrate, the second angle of inclination being greater than the first angle of inclination.

35. The display device of claim 33, wherein a lower portion of the active pattern fills the recess structure, a central portion of the active pattern contacts the source electrode and the drain electrode, and an inclined angle, relative to the substrate, of a sidewall of the central portion of the active pattern is greater than an inclined angle, relative to the substrate, of a sidewall of the lower portion of the active pattern.

36. The display device of claim 33, wherein the gate insulation layer has a level upper face, and a ratio between a depth of the recess structure and a thickness of the gate insulation layer is in a range from about 1.0:

1.7 to about 1.0;

30.0.

37. The display device of claim 33, wherein the gate insulation layer includes a stepped portion adjacent to the gate electrode, and a ratio between a depth of the recess structure and a thickness of the gate insulation layer is in a range from about 1.0:

1.7 to about 1.0;

10.0.

38. A method of manufacturing a display device, comprising:

forming a gate electrode on a substrate;

forming a gate insulation layer on the substrate to cover the gate electrode;

forming an electrode layer on the gate insulation layer;

forming a mask pattern on the electrode layer;

forming a source electrode and a drain electrode on the gate insulation layer by etching the electrode layer using the mask pattern;

forming a recess structure on the gate insulation layer and between the source electrode and the drain electrode;

forming an active pattern on the gate insulation layer, the source electrode and the drain electrode;

forming a first electrode electrically connected to the drain electrode;

forming a light emitting layer on the first electrode; and

forming a second electrode on the light emitting layer.

39. The method of claim 38, wherein the recess structure is formed by performing at least one of a plasma treatment or a cleaning treatment.

40. The method of claim 38, wherein the forming the recess structure further comprises:

forming a preliminary recess structure on the gate insulation layer by performing a plasma treatment on the gate insulation layer between the source electrode and the drain electrode;

removing the mask pattern from the source electrode and the drain electrode; and

performing a cleaning treatment on the gate insulation layer having the preliminary recess structure.

41. The method of claim 38, wherein the forming the recess structure further comprises:

forming a preliminary recess structure on the gate insulation layer by performing a plasma treatment on the gate insulation layer between the source electrode and the drain electrode;

forming the recess structure on the gate insulation layer by performing a cleaning treatment on the gate insulation layer having the preliminary recess structure; and

removing the mask pattern from the source electrode and the drain electrode.

42. The method of claim 38, wherein the forming the electrode layer further comprises:

forming a first electrode film on the gate insulation layer; and

forming a second electrode film on the first electrode film by nitriding the first electrode film,

wherein the forming the source electrode and the drain electrode further comprises;

partially etching the second electrode film and the first electrode film to form a first electrode pattern and a second electrode pattern on a first portion of the gate insulation layer and to form a third electrode pattern and a fourth electrode pattern on a second portion of the gate insulation layer, and

wherein the forming the recess structure further comprises;

removing the mask pattern from the source electrode and the drain electrode; and

performing at least one of a plasma treatment or a cleaning treatment on the gate insulation layer between the source electrode and the drain electrode.