SEMICONDUCTOR DEVICE HAVING REDUCED GATE CHARGES AND SUPERIOR FIGURE OF MERIT

• US 20120292696A1
• Filed: 05/18/2012
• Published: 11/22/2012
• Est. Priority Date: 05/18/2011
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Park, Chanho, Terrill, Kyle
• Granted Patent: US 11,114,559 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.

Claims

1. A semiconductor device comprising:

a first plurality of trench-like structures, each trench-like structure in said first plurality comprising a gate electrode contacted to gate metal and a source electrode contacted to source metal; and

a second plurality of disabled trench-like structures interleaved with said first plurality of trench-like structures.

2. The semiconductor device of claim 1 wherein each of said disabled trench-like structures comprises a single polysilicon region contacted to said source metal and contacted to gate metal.

3. The semiconductor device of claim 2 wherein said single polysilicon region is substantially in the same plane as said source electrode and said gate electrode.

4. The semiconductor device of claim 1 wherein said first plurality and said second plurality of trench-like structures are interleaved in alternating fashion.

5. The semiconductor device of claim 1 wherein at least two successive trench-like structures of said first plurality are separated from another trench-like structure of said first plurality by a disabled trench-like structure.

6. The semiconductor device of claim 1 comprising a layer of said source metal that traverses said first plurality of trench-like structures and said second plurality of trench-like structures, wherein said source electrode is contacted to said source metal outside an active core region of said semiconductor device and wherein said source electrode is insulated from said layer of source metal inside said active core region, and wherein said disabled trench-like elements are contacted to said layer of source metal inside said active core region.

7. The semiconductor device of claim 1 comprising a layer of said source metal that traverses said first plurality of trench-like structures and said second plurality of trench-like structures, wherein said gate electrode is situated between said source electrode and said layer of source metal, and wherein said gate electrode is insulated from said layer of source metal.

8. The semiconductor device of claim 1 wherein said first and second pluralities of trench-like structures are arranged in a pattern selected from the group consisting of:

one out of two trench-like structures are disabled;

one out of three trench-like structures are disabled;

one out of four trench-like structures are disabled.

9. The semiconductor device of claim 1 comprising a metal-oxide-semiconductor field-effect transistor (MOSFET).

10. The semiconductor device of claim 9 wherein said MOSFET comprises a high side MOSFET that is coupled to a low side MOSFET in a DC-to-DC converter.

11. A semiconductor device comprising:

a first split gate structure comprising a first electrode region and a second electrode region;

a second structure parallel to said first split gate structure and comprising a polysilicon region in contact with gate metal; and

a source metal layer that is insulated from said first split gate structure within an active region of said semiconductor device and is in contact with said polysilicon region within said active region.

12. The semiconductor device of claim 11 wherein said first electrode region comprises a source electrode contacted to source metal outside said active region, and wherein said second electrode comprises a gate electrode contacted to gate metal outside said active region.

13. The semiconductor device of claim 12 wherein said gate electrode is situated between said source electrode and said source metal layer, and wherein said gate electrode is insulated from said source metal layer and also from said source electrode.

14. The semiconductor device of claim 11 wherein said polysilicon region is substantially in the same plane as said first electrode region and said second electrode region.

15. The semiconductor device of claim 11 further comprising a second split gate structure comprising two electrode regions, wherein said second structure is situated between said first split gate structure and said second split gate structure.

16. The semiconductor device of claim 11 further comprising at least two successive split gate structures, each comprising two electrode regions, wherein said second structure is situated between said first split gate structure and said two successive split gate structures.

17. A semiconductor device comprising:

a first trench-like structure comprising a first polysilicon region and a second polysilicon region that are insulated from each other by an oxide region;

a second trench-like structure parallel to said first trench-like structure and comprising a third polysilicon region; and

a source metal layer that traverses both said first trench-like structure and said second trench-like structure, wherein said second polysilicon region is situated between said first polysilicon region and said source metal layer, and wherein said source metal layer is insulated from said second polysilicon region and is in contact with said third polysilicon region.

18. The semiconductor device of claim 17 wherein said first polysilicon region comprises a source electrode contacted to said source metal layer, wherein said second polysilicon region comprises a gate electrode contacted to gate metal, and wherein further said third polysilicon region is contacted to said source metal layer and to said gate metal.

19. The semiconductor device of claim 17 wherein said third polysilicon region is in the same plane as said first polysilicon region and said second polysilicon region.

20. The semiconductor device of claim 17 further comprising a third trench-like structure comprising two polysilicon regions, wherein said second trench-like structure is situated between said first trench-like structure and said third trench-like structure.

21. The semiconductor device of claim 17 further comprising at least two successive trench-like structures parallel to said first trench-like structure and said second trench-like structure, each of said successive trench-like structures comprising two electrode regions, wherein said second trench-like structure is situated between said first trench-like structure and said two successive trench-like structures.