HIGH-K METAL GATE DEVICE

• US 20120292719A1
• Filed: 05/19/2011
• Published: 11/22/2012
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.), International Business Machines Corporation
• Inventors: TEH, Young Way, AQUILINO, Michael V., SHEIKH, Arifuzzaman (Arif), TAN, Yun Ling, ZHANG, Hao, NAIR, Deleep R., LI, Jinghong H. (John)
• Granted Patent: US 8,853,796 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness T_E that is different from a thickness T_C at the central portion of the device region.

Claims

1. A method of forming a semiconductor device comprising:

providing a substrate prepared with a device region surrounded by an isolation region, the device region includes edge portions along a width direction of the device region and a central portion between the edge portions;

forming a gate electrode layer in the device region, wherein the gate electrode layer comprises a graded thickness in which a thickness T_E at edge portions of the device region is different from a thickness T_C at the central portion of the device region.

2. The method of claim 1 wherein forming the gate electrode with the graded thickness comprises:

protecting the central portion of the gate electrode with a mask which leaves edge portions of the gate electrode exposed; and

thinning edge portions of the gate electrode to the thickness T_E.

3. The method of claim 2 wherein the mask is formed by printing the active area mask smaller.

4. The method of claim 1 wherein forming the gate electrode with the graded thickness comprises providing the isolation region with a top surface above a top surface of the substrate to form a raised isolation region.

5. The method of claim 4 wherein the gate electrode layer is formed by PVD.

6. The method of claim 4 wherein the top surface of the isolation region is sufficiently above the top surface of the substrate to form the gate electrode layer with the graded thickness.

7. The method of claim 4 wherein the top surface of the isolation region is about 40-50 Å

higher than the top surface of the substrate.

8. The method of claim 1 wherein T_E is less than T_C.

9. The method of claim 8 wherein T_E is equal to about 30-40% of TC.

10. The method of claim 8 wherein T_E is sufficiently less than T_C to reduce V_T roll up.

11. The method of claim 8 wherein an edge portion is about 30% of an overall width of the device region.

12. The method of claim 8 wherein the graded thickness is a gradual change in thickness from T_C to T_E.

13. The method of claim 1 comprises forming a top gate electrode layer over the gate electrode layer.

14. A device comprising:

a substrate with a device region surrounded by an isolation region, the device region includes edge portions along a width of the device region and a central portion;

a gate layer disposed on the substrate over the device region, the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness T_E that is different from a thickness T_C at the central portion of the device region.

15. The device of claim 14 wherein the isolated region comprises a raised isolation region, the raised isolation region has a top surface above a top surface of the substrate.

16. The device of claim 14 wherein T_E is less than T_C.

17. The device of claim 16 wherein T_E is equal to about 30-40% of T_C.

18. The device of claim 16 wherein T_E is sufficiently less than T_C to reduce V_T roll up.

19. The device of claim 16 wherein an edge portion is about 30% of an overall width of the device region.

20. The device of claim 16 wherein the graded thickness is a gradual change in thickness from T_C to T_E.

21. The device of claim 14 comprises a top gate electrode layer over the gate electrode layer.

22. The device of claim 14 comprises a high-K dielectric layer below the gate electrode layer.

23. A device comprising:

a substrate;

a device region in the substrate;

an isolation region surrounding the device region, wherein the device region comprises;

an edge portion proximate the isolation region;

a central portion distal the isolation region; and

a gate electrode layer on the device region, wherein a thickness T_E of the gate electrode layer at the edge portion is different from a thickness T_C of the gate electrode layer at the central portion.