HVMOS Reliability Evaluation using Bulk Resistances as Indices

• US 20120293191A1
• Filed: 05/19/2011
• Published: 11/22/2012
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chia-Chung, Lu, Tse-Hua, Huang, Chi-Feng
• Granted Patent: US 9,209,098 B2
• Time in Patent Office: Days
• US Class Current: 324/691
• CPC Class Codes: G01R 27/08 Measuring resistance by measuring both voltage and current
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Claims

1. A method comprising:

determining a bulk resistance of a high-voltage PMOS (HVPMOS) device; and

evaluating a reliability of the HVPMOS device based on the bulk resistance.

2. The method of claim 1, wherein the bulk resistance is substantially proportional to a ratio of a source-to-bulk voltage of the HVPMOS device to a respective source current of the HVPMOS device.

3. The method of claim 2, wherein the bulk resistance is equal to the ratio, and is calculated with the source-to-bulk voltage being in a range between about 0.7V and about 0.8V.

4. The method of claim 3, wherein the step of determining the bulk resistance comprises:

measuring a plurality of source-to-bulk voltages of the HVPMOS device;

measuring a plurality of source currents of the HVPMOS device corresponding to the plurality of source-to-bulk voltages; and

selecting the bulk resistance among the plurality of source-to-bulk voltages, and the respective source current among the plurality of source currents and in the range.

5. The method of claim 2, wherein the step of determining the bulk resistance comprises simulating the bulk resistance.

6. The method of claim 1, wherein the step of evaluating the reliability of the HVPMOS device comprises comparing the bulk resistance with a reference bulk resistance, and wherein the HVPMOS device with the bulk resistance greater than the reference bulk resistance is determined as not reliable, and the HVPMOS device with the bulk resistance smaller than the reference bulk resistance is determined as reliable.

7. The method of claim 6 further comprising:

forming a plurality of HVPMOS devices in a same chip;

determining bulk resistances of the plurality of HVPMOS devices; and

comparing the bulk resistances with the reference bulk resistance, wherein HVPMOS devices with respective bulk resistances greater than the reference bulk resistance are determined as not reliable, and the HVPMOS devices with respective bulk resistances smaller than the reference bulk resistance are determined as reliable.

8. The method of claim 1 further comprising measuring an active-region-to-guard-ring spacing of the HVPMOS device, wherein the active-region-to-guard-ring spacing is a distance between an outer edge of an active region of the HVPMOS device and a nearest guard ring, wherein the active-region-to-guard-ring spacing is measured in a channel width direction of the HVPMOS device, and wherein the HVPMOS device with the active-region-to-guard-ring spacing greater than about 2 μ

m is determined as not reliable, and the HVPMOS device with the active-region-to-guard-ring spacing smaller than 2 μ

m is determined as reliable.

9. The method of claim 8 further comprising a step selected from the group consisting essentially of:

measuring an inner-GR-to-GR-spacing of the HVPMOS device, wherein the HVPMOS device with the inner-GR-to-GR-spacing greater than about 30 μ

m is determined as not reliable, and the HVPMOS device with the inner-GR-to-GR-spacing smaller than 30 μ

m is determined as reliable;

measuring an active-region-spacing of the HVPMOS device, wherein the HVPMOS device with the active-region-spacing greater than about 6 μ

m is determined as not reliable, and the HVPMOS device with the active-region-spacing spacing smaller than 6 μ

m is determined as reliable; and

measuring a width of an active region of the PMOS device, wherein the HVPMOS device with the width greater than about 10 μ

m is determined as not reliable, and the HVPMOS device with the with smaller than 10 μ

m is determined as reliable.

10. A method comprising:

determining a reference bulk resistance of a reference high-voltage PMOS (HVPMOS) device, wherein a parasitic lateral bipolar junction transistor (BJT) of the reference HVPMOS device has a current gain equal to about 1, and wherein the lateral BJT comprises a source, a drain, and a well region of the reference HVPMOS device as an emitter, a collector, and a base, respectively;

finding bulk resistances of a plurality of HVPMOS devices on a chip; and

evaluating reliability of the plurality of HVPMOS devices by comparing the bulk resistances with the reference bulk resistance.

11. The method of claim 10, wherein the step of evaluating reliability comprises comparing the bulk resistances with the reference bulk resistance, and wherein:

portions of the plurality of HVPMOS devices with bulk resistances greater than the reference bulk resistance are determined as not reliable; and

portions of the plurality of HVPMOS devices with bulk resistances smaller than the reference bulk resistance are determined as reliable.

12. The method of claim 10, wherein the reference bulk resistance and the bulk resistances are obtained by dividing source-to-bulk voltages by respective source currents of the respective reference HVPMOS device and the HVPMOS devices, and wherein the source-to-bulk voltages are in a range between about 0.7V and about 0.8V.

13. The method of claim 10, wherein the step of finding the bulk resistances comprises simulating the bulk resistances.

14. The method of claim 10 further comprising:

forming a plurality of sample HVPMOS devices, wherein active-region-to-guard-ring spacings of the plurality of sample HVPMOS devices are different from each other, and wherein the active-region-to-guard-ring spacings range from smaller than 2 μ

m to about 50 μ

m; and

finding among the plurality of HVPMOS devices the reference HVPMOS device by looking for the reference HVPMOS device having a current gain equal to about 1.

15. A device comprising:

a semiconductor chip, wherein all HVPMOS devices in the semiconductor chip and comprising adjacent guard rings have active-region-to-guard-ring spacings smaller than about 2 μ

m, wherein the active-region-to-guard-ring spacings are distances between outer edges of active regions of the respective HVPMOS devices and corresponding nearest n-type guard rings, and wherein the active-region-to-guard-ring spacings are measured in channel width directions of the respective HVPMOS devices.

16. The device of claim 15, wherein the semiconductor chip comprises a test structure comprising a plurality of HVPMOS devices, wherein each of the plurality of HVPMOS devices in the test structure is encircled by an adjacent guard ring, and wherein the plurality of HVPMOS devices is spaced apart from each other by guard rings.

17. The device of claim 15, wherein the semiconductor chip comprises a test structure comprising a plurality of HVPMOS devices forming a row, wherein the plurality of HVPMOS devices is encircled by a same adjacent guard ring, and wherein no guard ring separates the plurality of HVPMOS devices from each other.

18. The device of claim 15, wherein the semiconductor chip comprises a test structure comprising a plurality of HVPMOS devices formed as a plurality of rows, wherein the plurality of HVPMOS devices is encircled by a same adjacent guard ring, and wherein no guard ring separates the plurality of HVPMOS devices from each other.

19. The device of claim 15, wherein the all HVPMOS devices comprise a digital HVPMOS device and a radio-frequency HVPMOS device.