LOGIC CIRCUIT

• US 20120293209A1
• Filed: 05/09/2012
• Published: 11/22/2012
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TAKEWAKI, Yoshiya
• Granted Patent: US 8,779,799 B2
• Time in Patent Office: Days
• US Class Current: 326/103
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.

Claims

1. A logic circuit comprising:

first to fourth transistors;

fifth to eighth transistors;

a ninth transistor and a tenth transistor with gates electrically connected to each other; and

an eleventh transistor with one of a source and a drain electrically connected to the gates of the ninth transistor and the tenth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein a gate of the first transistor, a gate of the third transistor, and a gate of the eighth transistor are electrically connected to each other.

wherein a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to each other,

wherein a gate of the sixth transistor, a gate of the seventh transistor, the gate of the ninth transistor, and the gate of the tenth transistor are electrically connected to the one of the source and the drain of the eleventh transistor, where a node is formed,

wherein one of a source and a drain of the ninth transistor is electrically connected to the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fifth transistor and one of a source and a drain of the sixth transistor,

wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the third transistor and the other of the source and the drain of the fourth transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to one of a source and a drain of the seventh transistor and the other of the source and the drain of the eighth transistor,

wherein the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, the other of the source and the drain of the sixth transistor, and the other of the source and the drain of the seventh transistor are electrically connected to each other, and

wherein the eleventh transistor includes an oxide semiconductor.

2. The logic circuit according to claim 1, further comprising a capacitor electrically connected to the node.

3. The logic circuit according to claim 1, wherein switching to a NOR circuit or a NAND circuit is performed by switching a charge holding state at the node.

4. The logic circuit according to claim 1,

wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the ninth transistor are p-channel transistors, and

wherein the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the tenth transistor, and the eleventh transistor are n-channel transistors.

5. The logic circuit according to claim 1, wherein the oxide semiconductor includes at least one element selected from In, Ga, Sn, and Zn.

6. A logic circuit comprising:

first to fourth transistors;

fifth to eighth transistors;

a ninth transistor and a tenth transistor with gates electrically connected to each other; and

an eleventh transistor with one of a source and a drain electrically connected to the gates of the ninth transistor and the tenth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein a gate of the first transistor, a gate of the third transistor, and a gate of the eighth transistor are electrically connected to each other.

wherein a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to each other,

wherein a gate of the sixth transistor, a gate of the seventh transistor, the gate of the ninth transistor, and the gate of the tenth transistor are electrically connected to the one of the source and the drain of the eleventh transistor, where a node is formed,

wherein one of a source and a drain of the ninth transistor is electrically connected to the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fifth transistor and one of a source and a drain of the sixth transistor,

wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the third transistor and the other of the source and the drain of the fourth transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to one of a source and a drain of the seventh transistor and the other of the source and the drain of the eighth transistor,

wherein the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, the other of the source and the drain of the sixth transistor, and the other of the source and the drain of the seventh transistor are electrically connected to each other,

wherein the eleventh transistor includes an oxide semiconductor, and

wherein the eleventh transistor is stacked over the first to tenth transistors.

7. The logic circuit according to claim 6, further comprising a capacitor electrically connected to the node.

8. The logic circuit according to claim 6, wherein switching to a NOR circuit or a NAND circuit is performed by switching a charge holding state at the node.

9. The logic circuit according to claim 6,

wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the ninth transistor are p-channel transistors, and

wherein the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the tenth transistor, and the eleventh transistor are n-channel transistors.

10. The logic circuit according to claim 6, wherein the oxide semiconductor includes at least one element selected from In, Ga, Sn, and Zn.

11. A logic circuit comprising:

first to fourth transistors;

fifth to eighth transistors;

a ninth transistor and a tenth transistor with gates electrically connected to each other; and

an eleventh transistor with one of a source and a drain electrically connected to the gates of the ninth transistor and the tenth transistor,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the fifth transistor are electrically connected to a high potential power supply line,

wherein one of a source and a drain of the fourth transistor and one of a source and a drain of the eighth transistor are grounded or electrically connected to a low potential power supply line,

wherein a gate of the first transistor, a gate of the third transistor, and a gate of the eighth transistor are electrically connected to a first signal line.

wherein a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to a second signal line,

wherein a gate of the sixth transistor, a gate of the seventh transistor, the gate of the ninth transistor, and the gate of the tenth transistor are electrically connected to the one of the source and the drain of the eleventh transistor, where a node is formed,

wherein the other of the source and the drain of the eleventh transistor is electrically connected to a third signal line,

wherein a gate of the eleventh transistor is electrically connected to a fifth signal line,

wherein one of a source and a drain of the ninth transistor is electrically connected to the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fifth transistor and one of a source and a drain of the sixth transistor,

wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the third transistor and the other of the source and the drain of the fourth transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to one of a source and a drain of the seventh transistor and the other of the source and the drain of the eighth transistor,

wherein the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, the other of the source and the drain of the sixth transistor, and the other of the source and the drain of the seventh transistor are electrically connected to a fourth signal line, and

wherein the eleventh transistor includes an oxide semiconductor.

12. The logic circuit according to claim 11, further comprising a capacitor electrically connected to the node.

13. The logic circuit according to claim 11, wherein switching to a NOR circuit or a NAND circuit is performed by switching a charge holding state at the node.

14. The logic circuit according to claim 11,

wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the ninth transistor are p-channel transistors, and

wherein the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the tenth transistor, and the eleventh transistor are n-channel transistors.

15. The logic circuit according to claim 11, wherein the oxide semiconductor includes at least one element selected from In, Ga, Sn, and Zn.