Circuit, An Adjusting Method, and Use of a Control Loop

• US 20120293246A1
• Filed: 07/30/2012
• Published: 11/22/2012
• Est. Priority Date: 10/28/2008
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Dathe, Lutz, Vorwerk, Matthias, Hanusch, Thomas
• Granted Patent: US 8,525,583 B2
• Time in Patent Office: Days
• US Class Current: 327/544
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Claims

1. A circuit comprising:

a digital CMOS circuit having NMOS field-effect transistors and having PMOS field-effect transistors;

a first load device, wherein source terminals of the NMOS field-effect transistors of the digital CMOS circuit are connectable via the first load device to a first supply voltage;

a second load device, wherein source terminals of the PMOS field-effect transistors of the digital CMOS circuit are connectable via the second load device to a second supply voltage; and

an evaluation circuit configured to evaluate a first source voltage at the source terminals of the NMOS field-effect transistors, the evaluation circuit being connectable to the source terminals of the NMOS field-effect transistors, the evaluation circuit configured to evaluate a second source voltage at the source terminals of the PMOS field-effect transistors, the evaluation circuit being connectable to source terminals of the PMOS field-effect transistors,

wherein the evaluation circuit is configured to adjust a first voltage drop across the first load device and is connectable to a first control input of the first load device, and

wherein the evaluation circuit is configured to adjust a second voltage drop across the second load device and is connectable to a second control input of the second load device.

2. The circuit according to claim 1, wherein the circuit is configured to alternate between a sleep mode with a leakage current that flows through the digital circuit and an operating mode with an operating current that flows through the digital circuit, and wherein the operating current exceeds the leakage current

3. The circuit according to claim 1, wherein the evaluation circuit or the first load device has a first memory that is configured to store the adjustment of the first voltage drop, and/or the evaluation circuit or the second load device has a second memory configured to store the adjustment of the second voltage drop.

4. The circuit according to claim 1, wherein the first load device is configured to generate the first voltage drop via only a leakage current that flows through the digital CMOS circuit and the first load device.

5. The circuit according to claim 1, wherein the second load device is configured to generate the second voltage drop via only a leakage current that flows through the digital CMOS circuit and the second load device.

6. The circuit according to claim 1, wherein the evaluation circuit has a device for measuring a temperature, and wherein the evaluation circuit is configured to adjust the first voltage drop and/or to adjust the second voltage drop as a function of the measurement.

7. The circuit according to claim 1, wherein the first load device has an adjustable load comprising a plurality of transistors that act between the source terminals of the NMOS field-effect transistors and the first supply voltage and/or wherein the second load device has an adjustable load comprising a plurality of transistors that act between the source terminals of the PMOS field-effect transistors and the second supply voltage.

8. A method for adjusting a data retention voltage and/or a leakage current for a sleep mode of a CMOS circuit, the method comprising:

determining a first source voltage applied at source terminals of a NMOS field-effect transistor of the CMOS circuit;

determining a second source voltage applied at source terminals of a PMOS field-effect transistor of the CMOS circuit;

adjusting a first voltage drop across a first load device as a function of the first source voltage and/or the second source voltage, the first load device being connected to the source terminals of the NMOS field-effect transistor; and

adjusting a second voltage drop across a second load device as a function of the first source voltage and/or the second source voltage, the second load device being connected to the source terminals of the PMOS field-effect transistor.

9. The method according to claim 8, wherein the first load device is directly connected to the source terminals of the NMOS field-effect transistor;

and wherein the second load device is directly connected to the source terminals of the PMOS field-effect transistor.

10. A use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated for control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, wherein the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and wherein the adjustments of the control loop for the sleep mode are stored.