WORD LINE DIVIDER AND STORAGE DEVICE

• US 20120294061A1
• Filed: 05/16/2012
• Published: 11/22/2012
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: NAGATSUKA, Shuhei, MATSUZAKI, Takanori, INOUE, Hiroki
• Granted Patent: US 9,697,878 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A word line divider which has a simplified circuit structure and can operate stably is provided. A storage device which has a simplified circuit structure and can operate stably is provided. A transistor whose leakage current is extremely low is connected in series with a portion between a word line and a sub word line so that the word line divider is constituted. The transistor can include an oxide semiconductor for a semiconductor layer in which a channel is formed. Such a word line divider whose circuit structure is simplified is used in the storage device.

Claims

1. A word line divider comprising:

a word line;

a first sub word line;

a second sub word line;

a first transistor; and

a second transistor,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the word line,

wherein the other of the source and the drain of the first transistor is electrically connected to the first sub word line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second sub word line, and

wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×

10<sup>−

17</sup> A or lower.

2. The word line divider according to claim 1, wherein each of the first transistor and the second transistor comprises a channel, and the channel comprises an oxide semiconductor.

3. A storage device comprising the word line divider according to claim 1, comprising:

first memory cells electrically connected to the first sub word line; and

second memory cells electrically connected to the second sub word line.

4. The storage device according to claim 3, wherein each of the first memory cells and the second memory cells is a DRAM.

5. The storage device according to claim 3, wherein each of the first memory cells and the second memory cells is an SRAM.

6. The storage device according to claim 3,

wherein each of the first memory cells and the second memory cells including:

a third transistor comprising a channel comprising an oxide semiconductor; and

a capacitor electrically connected to one of a source and a drain of the third transistor, and

wherein a gate of the third transistor is electrically connected to one of the first sub word line and the second sub word line.

7. The storage device according to claim 3,

wherein each of the first memory cells and the second memory cells including:

a third transistor comprising a channel comprising an oxide semiconductor;

a fourth transistor; and

a capacitor,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the capacitor, and

wherein a gate of the third transistor is electrically connected to one of the first sub word line and the second sub word line.

8. A storage device comprising:

a first bit line;

a second bit line

a word line;

a first sub word line;

a second sub word line;

a first transistor;

a second transistor;

a first memory cell comprising a first data retention portion and a first selection transistor; and

a second memory cell comprising a second data retention portion and a second selection transistor,

wherein one of a source and a drain of the first selection transistor is electrically connected to the first bit line,

wherein one of a source and a drain of the second selection transistor is electrically connected to the second bit line,

wherein the other of the source and the drain of the first selection transistor is electrically connected to the first data retention portion,

wherein the other of the source and the drain of the second selection transistor is electrically connected to the second data retention portion,

wherein a gate of the first selection transistor is electrically connected to the first sub word line,

wherein a gate of the second selection transistor is electrically connected to the second sub word line,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the word line,

wherein the other of the source and the drain of the first transistor is electrically connected to the first sub word line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second sub word line, and

wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×

10<sup>−

17</sup> A or lower.

9. The storage device according to claim 8, wherein each of the first memory cell and the second memory cell is a DRAM.

10. The storage device according to claim 8, wherein each of the first memory cell and the second memory cell is an SRAM.

11. The storage device according to claim 8, wherein off-state leakage current per micrometer of channel width of each of the first selection transistor and the second selection transistor is 1×

10<sup>−

17</sup> A or lower.

12. The storage device according to claim 8, wherein each of the first selection transistor and the second selection transistor comprises a channel, and the channel comprises an oxide semiconductor.

13. The storage device according to claim 8,

wherein each of the first data retention portion and the second data retention portion comprises a capacitor electrically connected to the other of the source and the drain of the first selection transistor or the other of the source and the drain of the second selection transistor, and

wherein the first selection transistor and the second selection transistor comprising a channel comprising an oxide semiconductor.

14. The storage device according to claim 8,

wherein each of the first data retention portion and the second data retention portion comprises a third transistor and a capacitor,

wherein a gate of the third transistor and the capacitor are electrically connected to the other of the source and the drain of the first selection transistor or the other of the source and the drain of the second selection transistor, and

wherein the first selection transistor and the second selection transistor comprising a channel comprising an oxide semiconductor.

15. The storage device according to claim 8, wherein each of the first transistor and the second transistor comprises a channel, and the channel comprises an oxide semiconductor.

16. A word line divider comprising:

a word line;

a first sub word line;

a second sub word line;

a first transistor; and

a second transistor,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the word line,

wherein the other of the source and the drain of the first transistor is electrically connected to the first sub word line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second sub word line, and

wherein the first transistor and the second transistor comprise an oxide semiconductor.

17. A storage device comprising the word line divider according to claim 16, comprising:

first memory cells electrically connected to the first sub word line; and

second memory cells electrically connected to the second sub word line.

18. A storage device comprising:

a first bit line;

a second bit line

a word line;

a first sub word line;

a second sub word line;

a first transistor;

a second transistor;

a first memory cell comprising a first data retention portion and a first selection transistor; and

a second memory cell comprising a second data retention portion and a second selection transistor,

wherein one of a source and a drain of the first selection transistor is electrically connected to the first bit line,

wherein one of a source and a drain of the second selection transistor is electrically connected to the second bit line,

wherein the other of the source and the drain of the first selection transistor is electrically connected to the first data retention portion,

wherein the other of the source and the drain of the second selection transistor is electrically connected to the second data retention portion,

wherein a gate of the first selection transistor is electrically connected to the first sub word line,

wherein a gate of the second selection transistor is electrically connected to the second sub word line,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the word line,

wherein the other of the source and the drain of the first transistor is electrically connected to the first sub word line,

wherein the other of the source and the drain of the second transistor is electrically connected to the second sub word line, and

wherein the first transistor and the second transistor comprise an oxide semiconductor.

19. The storage device according to claim 18, wherein each of the first memory cell and the second memory cell is a DRAM.

20. The storage device according to claim 18, wherein each of the first memory cell and the second memory cell is an SRAM.

21. The storage device according to claim 18, wherein the first selection transistor and the second selection transistor comprise an oxide semiconductor.