Dynamic Level Shifter

• US 20120294095A1
• Filed: 05/16/2011
• Published: 11/22/2012
• Est. Priority Date: 05/16/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Shiu, Shinye
• Granted Patent: US 8,559,247 B2
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/225 Clock input buffers

Abstract

A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.

Claims

1. A circuit comprising:

a precharge circuit coupled to receive a clock signal, wherein the precharge circuit is configured to precharge an evaluation node to a first logic level during a first phase of the clock signal;

a pull-down circuit having an input node coupled to receive an input signal, wherein the pull-down circuit is configured to, during a second phase of the clock signal, provide a pull-down path between the evaluation and a ground node responsive to receiving the input signal at the first logic level; and

a keeper circuit, wherein the keeper circuit is configured to, during the second phase of the clock signal, hold the evaluation node at the first logic level responsive to the input node receiving the input signal at a second logic level;

wherein the first logic level, on the input node, is referenced to a first supply voltage, and wherein the first logic level, on the evaluation node, is referenced to a second supply voltage.

2. The circuit as recited in claim 1, wherein the precharge circuit is coupled to receive the clock signal from an output of a static level shifter circuit, wherein the clock signal is referenced to the second supply voltage.

3. The circuit as recited in claim 1, wherein the pull-down circuit includes:

first and second transistors coupled in series between the evaluation node and the ground node, wherein the first transistor includes a first gate terminal coupled to the input node, and wherein the second transistor includes a second gate terminal coupled to receive the clock signal;

wherein the keeper circuit includes;

third and fourth transistors, wherein the third transistor is coupled between a supply voltage node coupled to receive the second supply voltage and the fourth transistor, and wherein the fourth transistor is coupled between the third transistor and the evaluation node, wherein a gate terminal of the fourth transistor is coupled to the input node; and

an inverter having an input coupled to the evaluation node and an output coupled to a gate terminal of the third transistor.

4. The circuit as recited in claim 3, wherein the pull-down circuit is configured to activate the pull-down path responsive to activation of both the first and second transistors, wherein the first transistor is configured to be activated responsive to receiving, on its gate terminal, the input signal at the first logic level, and wherein the second transistor is configured to be activated responsive to the clock transitioning from the first phase to the second phase.

5. The circuit as recited in claim 1, wherein the pull-down circuit includes:

third, fourth, and fifth transistors coupled in series between the evaluation node and the ground node, wherein each of the third fourth and fifth transistors includes a respective gate terminal, wherein the third transistor is configured to be activated responsive to receiving the input signal at the first logic level on its gate terminal, wherein the fifth transistor is configured to be activated responsive to the clock signal transitioning to the second phase, and wherein the fourth transistor is configured to be activated at a delay time subsequent to the clock signal transitioning to the second phase;

wherein the keeper circuit includes;

fourth and fifth transistors, wherein the fourth transistor is coupled between a supply voltage node coupled to receive the second supply voltage and the fifth transistor, and wherein the fifth transistor is coupled between the fourth transistor and the evaluation node, wherein the fifth transistor is configured to be activated at the delay time subsequent to the clock signal transitioning to the second phase;

an inverter having an input coupled to the evaluation node and an output coupled to a gate terminal of the fourth transistor, wherein the fifth transistor is configured to be activated responsive the inverter driving the gate terminal of the fourth transistor to the second logic level; and

a sixth transistor coupled between the evaluation node and the ground node, the sixth transistor having a gate terminal coupled to the output of the inverter, wherein the sixth transistor is configured to be activated responsive to the inverter driving the gate terminal of the sixth transistors to the first logic level.

6. A level shifter comprising:

an evaluation node;

an inverter having an input coupled to the evaluation node;

a first transistor having a gate terminal coupled to an output of the inverter, a source terminal coupled to a first power supply voltage having a first magnitude during use, and a drain terminal;

a second transistor having a source terminal coupled to the drain terminal of the first transistor, and a drain terminal coupled to the evaluation node;

a precharge transistor having a source terminal coupled to the first power supply voltage, a drain terminal coupled to the evaluation node, and a gate terminal coupled to receive a clock signal, wherein the precharge transistor is configured to precharge the evaluation node to a first logic level during a first phase of the clock signal; and

an evaluation circuit coupled between the evaluation node and the ground node, wherein the evaluation circuit is configured to drive the evaluation node to a second logic level if activated during the second phase of the clock signal, wherein the evaluation circuit is coupled to an input node coupled to receive an input referenced to a second power supply voltage having a second magnitude during use, the second magnitude different from the first magnitude.

7. The level shifter as recited in claim 6, wherein the evaluation circuit further includes a third transistor having a gate terminal coupled to the input node, and a fourth transistor having a gate terminal coupled to receive the clock signal, wherein the third transistor is coupled to the evaluation node, and fourth transistor is coupled to a ground node.

8. The level shifter as recited in claim 7, wherein the third transistor is further coupled to the fourth transistor, wherein the evaluation circuit is configured to provide a pull-down path between the evaluation node and the ground node when the third and fourth transistors are both active, wherein the third transistor is configured to be activated responsive to receiving a signal at a first logic level on the input node, and wherein the fourth transistor is configured to be active responsive to the clock signal transitioning to the second phase;

and

wherein a gate terminal of the second transistor is coupled to the input node, wherein the second transistor is configured to be activated responsive to receiving the signal at a second logic level on the input node, and wherein the first transistor is configured to be activated responsive to the inverter driving its gate terminal to the second logic level.

9. The level shifter as recited in claim 7, wherein the evaluation circuit further includes a fifth transistor having a gate terminal coupled to receive a delayed version of the clock signal, and wherein a gate terminal of the second transistor is coupled to receive the delayed version of the clock signal, wherein the evaluation circuit is configured to provide a pull-down path between the evaluation node and ground responsive to activation of the third, fourth and fifth transistors;

wherein the third transistor is configured to be activated responsive to receiving a signal at the first logic level on the input node;

wherein the fourth transistor is configured to be activated responsive to receiving the clock signal at the first logic level; and

wherein the fifth transistor is configured to be activated responsive to receiving the delayed clock signal at the first logic level.

10. The level shifter as recited in claim 6, further comprising a sixth transistor having a gate terminal coupled to the output of the inverter, wherein the third transistor is coupled between the evaluation node and the ground node.

11. An integrated circuit comprising:

a processor core coupled to receive a first supply voltage;

a memory coupled to receive a second supply voltage; and

a static level shifter coupled to receive an input clock signal conveyed by the core, wherein the input clock signal is referenced to the first supply voltage, and wherein the static level shifter is configured to provide an output clock signal to the memory, wherein the output clock signal is referenced to the second supply voltage;

wherein the memory includes a plurality of dynamic level shifter circuits each coupled to receive a corresponding signal from the processor core,

wherein each of the dynamic level shifter circuits includes;

a transfer node;

a precharge circuit coupled to receive the output clock signal and configured to precharge the transfer node when the output clock signal is at a logic low level;

an evaluation circuit having an input node coupled to receive a corresponding one of a plurality of input signals from the processor core, wherein the evaluation circuit is configured to, when active, provide a pull-down path between the transfer node and a ground node;

a keeper circuit coupled between the evaluation node and the second voltage node, wherein the keeper circuit is configured to, when active, provide a keeper path between the transfer node and the second voltage node;

wherein the input signal is referenced to the first supply voltage, and wherein a signal on the transfer node is referenced to the second supply voltage.

12. The integrated circuit as recited in claim 11, wherein the evaluation circuit of each dynamic level shifter circuit includes a first transistor having a first gate terminal coupled to receive the corresponding one of the plurality of input signals and a second transistor having a second gate terminal coupled to receive the clock signal, wherein the first transistor is configured to be activated responsive to the receiving the corresponding one of the plurality of input signals as a logic high and wherein the second transistor is configured to be activated responsive to receiving the clock signal as a logic high

13. The integrated circuit as recited in claim 12, wherein the keeper circuit of each dynamic level shifter circuit includes:

an inverter having an input coupled to the transfer node;

a third transistor having a gate terminal coupled to an output of the inverter, wherein the third transistor is further coupled to the second voltage node, and wherein the third transistor is configured to be activated responsive to the inverter driving a logic low on its output;

a fourth transistor coupled between the third transistor and the transfer node.

14. The integrated circuit as recited in claim 13, wherein the evaluation circuit further includes, a fifth transistor coupled to receive a delayed version of the clock signal, wherein the fifth transistor is configured to be activated responsive to receiving the delayed version of the clock signal as a logic high;

wherein a gate terminal of the fourth transistor is coupled to receive the delayed version of the clock signal, wherein the fourth transistor is configured to be activated responsive to receiving the delayed version of the clock signal as a logic low; and

wherein the dynamic level shifter further includes a sixth transistor coupled between the transfer node and the ground node and having a gate terminal coupled to the output of the inverter, wherein the sixth transistor is configured to be activated responsive to the inverter driving its output high.

15. The integrated circuit as recited in claim 13, wherein the fourth transistor of each dynamic level shifter circuit is coupled to receive the corresponding one of the plurality of input signals, wherein the fourth transistor is configured to be activated responsive to receiving the corresponding one of the plurality of input signals as a logic low.

16. A method comprising:

a precharge circuit precharging an evaluation node of a dynamic level shifter circuit responsive to receiving a first clock signal at a logic low level on its respective gate terminal;

a pull-down circuit pulling the evaluation node to a logic low level when at least the first clock signal and an input signal are both at a logic high level;

a keeper circuit pulling the evaluation node to a logic high level when at least the evaluation node is at a logic high level; and

the dynamic level shifter circuit providing an output signal at a logic low signal when the evaluation node is at a logic high level and providing the output signal at a logic high level when the evaluation node is at a logic low level;

wherein the input signal is referenced to a first supply voltage, and wherein the output signal and a signal on the evaluation node are each referenced to a second supply voltage.

17. The method as recited in claim 16, wherein the first clock signal is referenced to the second supply voltage, and wherein the method further comprises:

a static level shifter receiving a second clock signal referenced to the first supply voltage; and

the static level shifter generating the first clock signal based on the second clock signal.

18. The method as recited in claim 16, further comprising activating the keeper circuit responsive to the keeper circuit receiving the input signal at a logic low level concurrent with the evaluation node being at a logic high level.

19. The method as recited in claim 16, further comprising:

activating the keeper circuit responsive to receiving a third clock signal at a logic low level concurrent with the evaluation signal being at a logic high level, wherein the third clock signal is a delayed version of the second clock signal; and

activating the pull-down circuit responsive to receiving the third clock signal at a logic high level concurrent with receiving the input signal and the second clock signal each at a logic high level.

20. The method as recited in claim 19, further comprising:

an inverter receiving a logic low on its input;

the inverter driving a logic high on its output responsive to receiving the logic low on its input;

activating a pull-down transistor responsive to the inverter driving a logic high on its output, the pull-down transistor being coupled between the evaluation node and a ground node and having a gate terminal coupled to the output of the inverter.

21. A dynamic level shifter comprising:

a first p-channel metal oxide semiconductor (PMOS) transistor coupled between an evaluation node and a first supply voltage node, wherein the first PMOS transistor is configured to be activated responsive to receiving a first clock signal as a logic low on a respective gate terminal;

a first inverter having an input coupled to the evaluation node;

a second PMOS transistor having a gate terminal coupled to an output of the inverter, the second PMOS transistor being further coupled to the first supply voltage node;

a third PMOS transistor coupled between the second PMOS transistor and the evaluation node;

a first n-channel metal oxide semiconductor (NMOS) transistor coupled to a return node and having a respective gate terminal coupled to receive the first clock signal, wherein the first NMOS transistor is configured to be activated responsive to receiving the first clock signal as a logic high on its respective gate terminal; and

a second NMOS transistor coupled to the evaluation node, the second NMOS transistor having a respective gate terminal coupled to receive an input signal, wherein the second NMOS transistor is configured to be activated responsive to receiving the input signal as a logic high;

wherein the first clock signal and a signal on the evaluation node are each referenced to a first supply voltage present on the first supply voltage node, and wherein the input signal is referenced to a second supply voltage having a magnitude less than the first supply voltage.

22. The dynamic level shifter as recited in claim 21, wherein the second NMOS transistor is coupled between the first NMOS transistor and the evaluation node.

23. The dynamic level shifter as recited in claim 22, wherein a gate terminal of the third PMOS transistor is coupled to receive the input signal.

24. The dynamic level shifter as recited in claim 21, further comprising a third NMOS transistor coupled between the first and second NMOS transistors, wherein a gate terminal of the third NMOS transistor is coupled to receive a second clock signal, wherein the second clock signal is a delayed version of the first clock signal, and wherein a gate terminal of the third PMOS transistor is coupled to receive the second clock signal.

25. The dynamic level shifter as recited in claim 21, further comprising a second having an input coupled to the evaluation node and an output coupled to an output node.