ARRAYS OF LONG NANOSTRUCTURES IN SEMICONDUCTOR MATERIALS AND METHODS THEREOF

• US 20120295074A1
• Filed: 11/17/2011
• Published: 11/22/2012
• Est. Priority Date: 11/19/2010
• Status: Active Grant

• Current Assignee: Synergy Thermogen Incorporated
• Original Assignee: Alphabet Energy, Inc.
• Inventors: Yi, Mingqiang, Scullin, Matthew L., Lee, Chii Guang, Muckenhirn, Sylvain, Matus, Gabriel Alejandro, Hilken, Dawn L.
• Granted Patent: US 9,240,328 B2
• Time in Patent Office: Days
• US Class Current: 428/195.1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 31/035227 the quantum structure being quantum wires, or nanorods carbon nanotubes H10K85/211
• CPC Class Codes: H10N 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
• CPC Class Codes: Y10T 428/249924 Noninterengaged fiber-containing paper-free web or sheet which is not of specified porosity
• CPC Class Codes: Y10T 428/2913 Rod, strand, filament or fiber

Abstract

An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 μm. All nanowires of the plurality of nanowires are substantially parallel to each other.

Claims

1. An array of nanowires, the array comprising:

a plurality of nanowires, the plurality of nanowires including a plurality of first ends and a plurality of second ends respectively;

wherein;

for each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 μ

m; and

all nanowires of the plurality of nanowires are substantially parallel to each other.

2. The array of nanowires of claim 1 wherein the distance is at least 300 μ

m.

3. The array of nanowires of claim 2 wherein the distance is at least 400 μ

m.

4. The array of nanowires of claim 3 wherein the distance is at least 500 μ

m.

5. The array of nanowires of claim 4 wherein the distance is at least 525 μ

m.

6. The array of nanowires of claim 1 wherein each of the plurality of nanowires includes a semiconductor material.

7. The array of nanowires of claim 6 wherein the semiconductor material is silicon.

8. An array of nanostructures, the array comprising:

a plurality of nanostructures, the plurality of nanostructures including a plurality of first ends and a plurality of second ends respectively;

wherein;

for each of the plurality of nanostructures, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 μ

m;

all nanostructures of the plurality of nanostructures are substantially parallel to each other; and

each of the plurality of nanostructures includes a semiconductor material.

9. The array of nanostructures of claim 8 wherein the semiconductor material is silicon.

10. The array of nanostructures of claim 8 wherein the distance is at least 300 μ

m.

11. The array of nanostructures of claim 10 wherein the distance is at least 400 μ

m.

12. The array of nanostructures of claim 11 wherein the distance is at least 500 μ

m.

13. The array of nanostructures of claim 12 wherein the distance is at least 525 μ

m.

14. The array of nanostructures of claim 8 wherein the plurality of nanostructures corresponds to a plurality of nanoholes respectively.

15. An array of nanowires, the array comprising:

a plurality of nanowires, each of the plurality of nanowires including a first end at a first surface and a second end, the first end and the second end being separated by a first distance of at least 200 μ

m;

wherein;

the plurality of nanowires corresponds to a first area on the first surface; and

all nanowires of the plurality of nanowires are substantially parallel to each other.

16. The array of nanowires of claim 15 wherein the plurality of nanowires is a part of a thermoelectric device.

17. The array of nanowires of claim 15 wherein the first distance is at least 300 μ

m.

18. The array of nanowires of claim 17 wherein the first distance is at least 400 μ

m.

19. The array of nanowires of claim 18 wherein the first distance is at least 500 μ

m.

20. The array of nanowires of claim 19 wherein the first distance is at least 525 μ

m.

21. The array of nanowires of claim 15 wherein the first area is at least 100 mm² in size.

22. The array of nanowires of claim 21 wherein the first area is at least 1000 mm² in size.

23. The array of nanowires of claim 22 wherein the first area is at least 2500 mm² in size.

24. The array of nanowires of claim 23 wherein the first area is at least 5000 mm² in size.

25. The array of nanostructures of claim 15 wherein each of the plurality of nanostructures are substantially perpendicular to the first surface.

26. The array of nanowires of claim 15 wherein each of the plurality of nanowires corresponds to a cross-sectional area associated with a distance across, the distance across being less than 250 nm.

27. The array of nanowires of claim 26 wherein the cross-sectional area is substantially uniform along a longitudinal direction for each of the plurality of nanowires.

28. The array of nanowires of claim 15 wherein the plurality of nanowires includes a first nanowire and a second nanowire, the first nanowire and the second nanowire being separated by a second distance, the second distance being less than 1000 nm.

29. The array of nanowires of claim 15 wherein each of the plurality of nanowires is separated from another nanowire selected from the plurality of nanowires by a second distance, the second distance being less than 1000 nm.

30. The array of nanowires of claim 15 wherein each of the plurality of nanowires includes a semiconductor material.

31. The array of nanowires of claim 30 wherein the semiconductor material is silicon.

32. An array of nanostructures, the array comprising:

a plurality of nanostructures, each of the plurality of nanostructures including a first end at a first surface and a second end, the first end and the second end being separated by a first distance of at least 200 μ

m;

wherein;

the plurality of nanostructures corresponds to a first area on the first surface;

all nanostructures of the plurality of nanostructures are substantially parallel to each other; and

each of the plurality of nanostructures includes a semiconductor material.

33. The array of nanostructures of claim 32 wherein the plurality of nanowires is a part of a thermoelectric device.

34. The array of nanostructures of claim 32 wherein the semiconductor material is silicon.

35. The array of nanostructures of claim 32 wherein the first distance is at least 300 μ

m.

36. The array of nanostructures of claim 35 wherein the first distance is at least 400 μ

m.

37. The array of nanostructures of claim 36 wherein the first distance is at least 500 μ

m.

38. The array of nanostructures of claim 37 wherein the first distance is at least 525 μ

m.

39. The array of nanostructures of claim 32 wherein the first area is at least 100 mm² in size.

40. The array of nanostructures of claim 39 wherein the first area is at least 1000 mm² size.

41. The array of nanostructures of claim 40 wherein the first area is at least 2500 mm² size.

42. The array of nanostructures of claim 41 wherein the first area is at least 5000 mm² in size.

43. The array of nanostructures of claim 32 wherein each of the plurality of nanostructures are substantially perpendicular to the first surface.

44. The array of nanostructures of claim 32 wherein the plurality of nanostructures corresponds to a plurality of nanoholes respectively.

45. The array of nanostructures of claim 44 wherein each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, the distance across being less than 250 nm.

46. The array of nanostructures of claim 45 wherein the cross-sectional area is substantially uniform along a longitudinal direction for each of the plurality of nanoholes.

47. The array of nanostructures of claim 32 wherein the plurality of nanostructures includes a first nanostructure and a second nanostructure, the first nanostructure and the second nanostructure being separated by a second distance, the second distance being less than 1000 nm.

48. The array of nanostructures of claim 32 wherein each of the plurality of nanostructures is separated from another nanostructure selected from the plurality of nanostructures by a second distance, the second distance being less than 1000 nm.

49. A method for forming an array of nanowires, the method comprising:

providing a semiconductor substrate including a first surface and one or more second surfaces;

masking at least one or more portions of the one or more second surfaces with at least a first portion of the first surface being exposed;

applying a metalized film to at least the exposed first portion of the first surface;

etching the semiconductor substrate through at least the exposed first portion of the first surface using a first etchant solution; and

forming a first plurality of nanowires, each of the first plurality of nanowires including a first end at a third surface and a second end, the first end and the second end being separated by a first distance of at least 200 μ

m;

wherein;

the first plurality of nanowires corresponds to a first area on the first surface;

the first area on the first surface substantially corresponds to the exposed first portion of the first surface; and

all nanowires of the first plurality of nanowires are substantially parallel to each other.

50. The method of claim 49 wherein the semiconductor substrate includes silicon.

51. The method of claim 49 wherein the process for masking at least one or more portions of the one or more second surfaces includes applying one or more masking materials to the one or more second surfaces.

52. The method of claim 51 wherein the one or more masking materials are selected from a group consisting of tape, nail polish, photo resist, Si₃N₄, SiC, DLC, Al, Ti, Ni, Au, Ag, Cr, ITO, Fe, Pt, and Mo.

53. The method of claim 49 wherein the metalized film includes one or more metals selected from a group consisting of Ag, Au, Pt, Pd, Ni, and Cu.

54. The method of claim 49 wherein the first etchant solution includes one or more oxidizing agents.

55. The method of claim 54 wherein the one or more oxidizing agents are selected from a group consisting of AgNO₃, KNO₃, NaNO₃, Fe(NO₃)₃, H₂O₂, Ag₂CrO₄, HNO₃, and KMnO₄.

56. The method of claim 49, and further comprising etching the semiconductor substrate through at least the exposed portion of the first surface using a second etchant solution, the second etchant solution being different from the first etchant solution.

57. The method of claim 49, and further comprising washing the semiconductor substrate.

58. The method of claim 49, and further comprising, after the process for forming a first plurality of nanowires, cleaning the semiconductor substrate.

59. The method of claim 49, and further comprising, after the process for forming a first plurality of nanowires, drying the semiconductor substrate.

60. The method of claim 49 wherein:

the semiconductor substrate includes a fourth surface opposite to the first surface; and

the process for masking at least one or more portions of the one or more second surfaces includes keeping at least a second portion of the fourth surface exposed.

61. The method of claim 60, and further comprising:

applying the metalized film to at least the exposed second portion of the fourth surface;

etching the semiconductor substrate through at least the exposed second portion of the fourth surface using the first etchant solution; and

forming a second plurality of nanowires, each of the second plurality of nanowires including a third end at a fifth surface and a fourth end, the fifth surface being different from the third surface.