RESISTOR MATRIX OFFSET COMPENSATION

• US 20120296588A1
• Filed: 05/19/2011
• Published: 11/22/2012
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Dietz, Paul
• Granted Patent: US 8,706,432 B2
• Time in Patent Office: Days
• US Class Current: 702/65
• CPC Class Codes: G06F 3/04144 using an array of force sensing means position sensing using the local deformation of sensor cells G06F3/0447
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184

Abstract

A method of measuring resistance in each of a plurality of resistors in a resistor matrix is provided. Each resistor is located at a different intersection between a column conductor and a row conductor. The, the method includes determining an offset error row current of each row conductor, scanning each row conductor to identify if that row conductor is connected to a column conductor by one of the plurality of resistors, if that row conductor is connected to a column conductor by one of the plurality of resistors, scanning each resistor connected to that row conductor to determining if that resistor is connecting a column conductor to that row conductor, and if that resistor is connecting a column conductor to that row conductor, outputting an offset compensated resistance of that resistor calculated from the row current measured for that resistor less the offset error row current for that row conductor.

Claims

1. A method of measuring resistance in each of a plurality of resistors arranged in a resistor matrix, each resistor being located at a different intersection between a column conductor and a row conductor, and each resistor selectively connecting that column conductor to that row conductor with a variable resistance, the method comprising:

determining an offset error row current of each row conductor;

scanning each row conductor to identify if that row conductor is connected to a column conductor by one of the plurality of resistors;

if that row conductor is connected to a column conductor by one of the plurality of resistors, scanning each resistor connected to that row conductor to determining if that resistor is connecting a column conductor to that row conductor; and

if that resistor is connecting a column conductor to that row conductor, outputting an offset compensated resistance of that resistor calculated from the row current measured for that resistor less the offset error row current for that row conductor.

2. The method of claim 1, wherein scanning each row conductor includes applying a test voltage to all column conductors that can be connected to that row conductor, applying a different test voltage to that row conductor, measuring a row current of that row conductor, and identifying that row conductor as being connected to a column conductor by one of the plurality of resistors if the row current of that row conductor is greater than a current threshold.

3. The method of claim 1, wherein determining an offset error row current for each row conductor includes for a given row conductor, applying a same voltage to all column conductors that can be connected to that row conductor and that row conductor, and measuring an offset error row current of that row conductor.

4. The method of claim 3, wherein determining the offset error row current for each row conductor includes for a given row conductor, measuring the offset error row current prior to scanning each resistor connected to that row conductor to determine if that resistor is connecting a column conductor to that row conductor and measuring the offset error row current upon completion of scanning each resistor connected to that row conductor, and linearly interpolating the offset error row current in accordance with both offset error row current measurements.

5. The method of claim 1, wherein scanning each resistor connected to that row conductor to determine if that resistor is connecting a column conductor to that row conductor includes applying a test voltage to a column conductor connected to that resistor, applying a different voltage to the row conductor and all other column conductors that can be connected to that row conductor, measuring a row current of that row conductor, and identifying that row conductor as being connected to a column conductor by that resistor if the row current is greater than a threshold current.

6. The method of claim 1, further comprising:

subsequent to outputting the offset compensated resistance of resistors that connect a column conductor to a row conductor, determining an offset error row current of each row conductor;

subsequent to outputting the offset compensated resistance of resistors that connect a column conductor to a row conductor, scanning each row conductor in which a resistor did not connect a column conductor to that row conductor in the previous scan to identify if that row conductor is connected to a column conductor by one of a plurality of newly connecting resistors that did not connect a column conductor to that row conductor in a previous scan;

if that row conductor is connected to a column conductor by one of the plurality of newly connecting resistors, or that row conductor was connected to a column conductor by one of the plurality of resistors in the previous scan, scanning each resistor connected to that row conductor to determine if that resistor is connecting a column conductor to that row conductor; and

if that resistor is connecting a column conductor to that row conductor, outputting an offset compensated resistance of that resistor calculated from the row current measured for that resistor less the offset error row current for that row conductor.

7. The method of claim 6, wherein scanning each row conductor in which a resistor did not connect a column conductor to that row conductor in the previous scan includes applying a test voltage to column conductors that were not connected to that row conductor by one of the plurality of resistors in the previous scan, applying a different test voltage to the row conductor and column conductors that were connected to that row conductor by one of the plurality of resistors in the previous scan, measuring a row current of that row conductor, and identifying that row conductor as being connected to a column conductor by one of the plurality of resistors if the row current of that row conductor is greater than a current threshold.

8. The method of claim 1, wherein the measurement circuit includes a transimpedance amplifier for each row conductor.

9. A computing device, comprising:

a resistor matrix including a plurality of resistors each being located at a different intersection between a column conductor and a row conductor, and each resistor selectively connecting that column conductor to that row conductor with a variable resistance;

a measurement circuit to measure a row current of each row conductor of the resistor matrix;

a scanning subsystem holding instructions executable to;

determine an offset error row current for each row conductor;

scan each row conductor to identify if that row conductor is connected to a column conductor by one of the plurality of resistors;

if that row conductor is connected to a column conductor by one of the plurality of resistors, scan each resistor connected to that row conductor to determine if that resistor is connecting a column conductor to that row conductor; and

if that resistor is connecting a column conductor to that row conductor, output an offset compensated resistance of that resistor calculated from the row current measured for that resistor less the offset error row current for that row conductor.

10. The computing device of claim 9, wherein scanning each row conductor to identify if that row conductor is connected to a column conductor by one of the plurality of resistors includes applying a test voltage to all column conductors that can be connected to that row conductor, applying a different test voltage to that row conductor, measuring a row current of that row conductor, and identifying that row conductor as being connected to a column conductor by one of the plurality of resistors if the row current of that row conductor is greater than a current threshold.

11. The computing device of claim 9, wherein determining an offset error row current for each row conductor includes for a given row conductor, applying a same voltage to all column conductors that can be connected to that row conductor and that row conductor, and measuring an offset error row current of that row conductor.

12. The computing device of claim 11, wherein determining the offset error row current for each row conductor includes for a given row conductor, measuring the offset error row current prior to scanning each resistor connected to that row conductor to determine if that resistor is connecting a column conductor to that row conductor and measuring the offset error row current upon completion of scanning each resistor connected to that row conductor, and linearly interpolating the offset error row current in accordance with both offset error row current measurements.

13. The computing device of claim 9, wherein scanning each resistor connected to that row conductor to determine if that resistor is connecting a column conductor to that row conductor includes applying a test voltage to a column conductor connected to that resistor, applying a different voltage the row conductor and to all other columns conductors that can be connected to that row conductor, measuring a row current of that row conductor, and identifying that row conductor as being connected to a column conductor by that resistor if the row current is greater than a threshold current.

14. The computing device of claim 9, wherein the scanning subsystem further holds instructions executable to:

subsequent to outputting the offset compensated resistance of resistors that connect a column conductor to a row conductor, determine an offset error row current of that row conductor;

subsequent to outputting the offset compensated resistance of resistors that connect a column conductor to a row conductor, scan each row conductor in which a resistor did not connect a column conductor to that row conductor in the previous scan to identify if that row conductor is connected to a column conductor by one of a plurality of newly connecting resistors that did not connect a column conductor to that row conductor in a previous scan;

if that row conductor is connected to a column conductor by one of the plurality of newly connecting resistors, or that row conductor was connected to a column conductor by one of the plurality of resistors in the previous scan, scan each resistor connected to that row conductor to determine if that resistor is connecting a column conductor to that row conductor; and

if that resistor is connecting a column conductor to that row conductor, output an offset compensated resistance of that resistor calculated from the row current measured for that resistor less the offset error row current for that row conductor.

15. The computing device of claim 14, wherein scanning each row conductor in which a resistor did not connect a column conductor to that row conductor in the previous scan includes applying a test voltage to column conductors that were not connected to that row conductor by one of the plurality of resistors in the previous scan, applying a different test voltage the row conductor and to column conductors that were connected to that row conductor by one of the plurality of resistors in the previous scan, measuring a row current of that row conductor, and identifying that row conductor as being connected to a column conductor by one of the plurality of resistors if the row current of that row conductor is greater than a current threshold.

16. The computing device of claim 9, wherein the measurement circuit includes a transimpedance amplifier for each row conductor.

17. A computing device, comprising:

a resistor matrix including a plurality of pressure-sensitive resistors each being located at a different intersection between a column conductor and a row conductor, and each pressure-sensitive resistor selectively connecting that column conductor to that row conductor with a variable resistance;

a measurement circuit to measure a row current of each row conductor of the resistor matrix;

a scanning subsystem holding instructions executable to;

determine an offset error row current for a row conductor; and

if a pressure-sensitive resistor is connecting a column conductor to the row conductor, output an offset compensated resistance of that pressure-sensitive resistor calculated from the row current measured for that pressure-sensitive resistor less the offset error row current for the row conductor.

18. The computing device of claim 17, wherein the resistor matrix includes a first layer comprising the plurality of column conductors;

and a second layer, opposing the first layer, comprising the plurality of row conductors, the first layer and/or the second layer being flexible to locally and temporarily deform when force is applied to connect a column conductor to a row conductor.

19. The computing device of claim 17, wherein determining an offset error row current for that row conductor includes applying a same voltage to all column conductors that can be connected to that row conductor and that row conductor, and measuring an offset error row current of that row conductor.

20. The computing device of claim 17, wherein the measurement circuit includes a transimpedance amplifier.