STORAGE SUBSYSTEM

• US 20120297244A1
• Filed: 07/16/2012
• Published: 11/22/2012
• Est. Priority Date: 05/25/2009
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: KITAHARA, Jun, TAKADA, Masanori, SUGIMOTO, Sadahiro
• Granted Patent: US 8,549,381 B2
• Time in Patent Office: Days
• US Class Current: 714/6.22
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/1054 Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

Claims

1. A storage system, comprising:

a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group; and

a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices,

wherein a first flash memory controller of the first flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

2. A storage system according to claim 1, wherein the storage controller creates an XOR write command for carrying out an XOR write to the first flash memory device, and transfers the created XOR write command to the first flash memory controller, and

the first flash memory controller, upon receiving the XOR write command, reads out from the first flash memory device an old parity specified by the XOR write command, creates a new parity by carrying out an exclusive OR operation based on the read-out old parity and a plurality of data attached to the XOR write command, and writes the created new parity to the first flash memory device.

3. The storage system according to claim 1, wherein the storage controller adds to the XOR write command a physical address of the old parity and a physical address of the new parity, as well as the old data and the new data, which are targeted for data updating,

the first flash memory controller reads out the old parity from the first flash memory device in accordance with the old parity physical address added to the XOR wrote command, creates a new parity by carrying out an exclusive OR operation using the read-out old parity, and the old data and the new data added to the XOR write command, and stores the created new parity in a page belonging to a renewal area of the first flash memory device in accordance with the physical address of the new parity added to the XOR write command.

4. The storage system according to claim 1, wherein

the first flash memory controller transfers to the storage controller in response to the XOR write command a status denoting the outcome of processing specified by the XOR write command, and

the storage controller, upon receiving a completion status as the status from the first flash memory controller, completes the processing in accordance with the creation of the XOR write command, and upon receiving an error status as the status from the first flash memory controller, creates a new XOR write command for writing a new parity to a new renewal area of the first flash memory device, transfers the newly created XOR write command to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the newly created XOR write command.

5. The storage subsystem according to claim 1, wherein

the first flash memory controller transfers to the storage controller in response to the XOR write command a status denoting the outcome of processing specified by the XOR write command, and

the storage controller determines whether or not the first flash memory controller has a malfunction when the status has not been returned from the storage controller within a fixed time period, and

when the first flash memory controller has a malfunction, creates a parity from a plurality of data, executes a correction copy for copying the created parity to a spare flash memory device, creates a new XOR write command for writing the new parity to a new renewal area of the spare flash memory device, transfers the newly created XOR write command to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the newly created XOR write command, and

when the first flash memory controller is normal, and on a condition that new parity addition information written to the first flash memory device is normal, completes the processing in accordance with the creation of the XOR write command, based on determination that the new parity has been written normally to the first flash memory device.

6. The storage system according to claim 1, wherein

the first flash memory controller transfers to the storage controller in response to the XOR write command a status denoting the outcome of processing specified by the XOR write command, and

the storage controller determines whether or not the first flash memory controller has a malfunction when the status has not been returned from the storage controller within a fixed time period,

when the first flash memory controller has a malfunction, creates a parity from a plurality of data, executes a correction copy for copying the created parity to a spare flash memory device, creates a new XOR write command for writing the new parity to a new renewal area of the spare flash memory device, transfers the newly created XOR write command to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the newly created XOR write command,

when the first flash memory controller is normal, determines whether or not new parity addition information written normally to the first flash memory device,

when the new parity addition information is written normally, completes the processing in accordance with the creation of the XOR write command, based on determination that the new parity has been written normally to the first flash memory device, and

when the new parity addition information is not written normally, determines whether or not the renewal area to be stored with the new parity, from among the renewal areas of the first flash memory device, has been erased, when the renewal area to be stored with the new parity has been erased, creates a new XOR write command for writing the new parity to the renewal area to be stored with the new parity, transfers the newly created XOR write command to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the newly created XOR write command, and

when the renewal area to be stored with the new parity has not been erased, creates a new XOR write command for writing the new parity to a renewal area that is different from the renewal area to be stored with the new parity, transfers the newly created XOR write command to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the newly created XOR write command.

7. The storage subsystem according to claim 1, wherein

the first flash memory controller comprises a status recording memory for sequentially recording a status in which data input/output processing to/from the first flash memory device,

the first flash memory controller transfers contents recorded in the status recording memory to the storage controller, and

the storage controller, upon receiving contents recorded in the status recording memory from the first flash memory controller, creates instruction information based on the received contents, transfers the created instruction information to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the instruction information.

8. The storage subsystem according to claim 1, wherein

the first flash memory controller comprises a status recording memory for sequentially recording a status in which data input/output processing to/from the first flash memory device is carried out,

the first flash memory controller transfers contents recorded in the status recording memory to the storage controller, and

the storage controller, upon receiving from the first flash memory controller, as the contents recorded in the status recording memory, information denoting that processing has been canceled prior to the start of writing of the new parity write, creates on the basis of the received contents a new XOR write command for writing a new parity to the same renewal area of the first flash memory device, creates instruction information including the newly created XOR write command, transfers the created instruction information to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the instruction information.

9. The storage subsystem according to claim 1, wherein

the first flash memory controller comprises a status recording memory for sequentially recording a status in which data input/output processing to/from the first flash memory device is carried out,

the first flash memory controller transfers contents recorded in the status recording memory to the storage controller, and

the storage controller, upon receiving from the first flash memory controller, as the contents recorded in the status recording memory, information denoting that processing has been canceled prior to the completion of writing of the new parity, creates on the basis of the received contents a new XOR write command for writing a new parity to a new renewal area of the first flash memory device, creates instruction information including the newly created XOR write command, transfers the created instruction information to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the instruction information.

10. The storage subsystem according to claim 1, wherein

the first flash memory controller comprises a status recording memory for sequentially recording a status in which data input/output processing to/from the first flash memory device is carried out,

the first flash memory controller transfers contents recorded in the status recording memory to the storage controller, and

the storage controller, upon receiving from the first flash memory controller, as the contents recorded in the status recording memory, information denoting that processing has been canceled prior to pointer renewal, creates, on the basis of the received contents, instruction information for carrying out the pointer renewal, transfers the created instruction information to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the instruction information.

11. The storage subsystem according to claim 1, wherein

the first flash memory controller comprises a status recording memory for sequentially recording a status in which data input/output processing to/from the first flash memory device is carried out,

the first flash memory controller transfers contents recorded in the status recording memory to the storage controller, and

the storage controller, upon receiving from the first flash memory controller, as the contents recorded in the status recording memory, information denoting that processing has been canceled prior to a status report, creates, on the basis of the received contents, instruction information to the effect that the processing for writing the new parity has completed normally, transfers the created instruction information to the first flash memory controller, and instructs the first flash memory controller to carry out processing in accordance with the instruction information.

12. The storage system according to claim 1, further comprising:

a second flash memory controller of a second flash memory device of the plurality of flash memory devices, the second flash memory controller being configured to send old data, that is updated with the data, in the second flash memory device to the storage controller,

wherein the storage controller is configured to receive the old data and send the data and the old data to the first flash memory device, and

wherein the first flash memory controller is configured to receive the data and the old data and create a new parity on the basis of the data, the old data and old parity in the first flash memory device.

13. The storage system according to claim 12,

wherein each of the flash memory chips is configured of a plurality of blocks each including a plurality of pages, and

wherein each flash memory controller deletes data in units of the blocks and read and write the data in units of the pages.