SEMICONDUCTOR CHIP AND TEST METHOD

• US 20120297263A1
• Filed: 05/17/2012
• Published: 11/22/2012
• Est. Priority Date: 05/18/2011
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: TAYA, Takashi
• Granted Patent: US 8,667,353 B2
• Time in Patent Office: Days
• US Class Current: 714/733
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor chip having a functional block that performs a communication function includes an input circuit that supplies an oscillating test signal to the functional block, and a test circuit that detects the strength of an oscillating signal which the functional block outputs in response. A strength signal indicating the detected strength is output from the test circuit through an external terminal of the semiconductor chip to a test device. The test device evaluates the strength signal to decide whether an operating characteristic of the functional block is within a specified range. The strength information indicated by the strength signal is not affected by impedance on the signal transmission line between the semiconductor chip and the test device, so the test is not affected by impedance loss.

Claims

1. A semiconductor chip comprising:

a functional block for generating an oscillating output signal to perform a communication function;

an input circuit for supplying an oscillating test signal to the functional block, thereby causing the functional block to generate the oscillating output signal;

a test circuit for detecting a first strength, the first strength being a strength of the oscillating output signal generated by the functional block in response to input of the oscillating test signal, and generating a strength signal indicating the first strength; and

a first external terminal for external output of the strength signal.

2. The semiconductor chip of claim 1, wherein the strength signal is a direct-current signal.

3. The semiconductor chip of claim 1, wherein the strength signal is a direct-current voltage signal.

4. The semiconductor chip of claim 1, wherein the strength signal is a digital signal.

5. The semiconductor chip of claim 1, wherein the test circuit also detects a second strength, the second strength being a strength of the oscillating test signal.

6. The semiconductor chip of claim 5, wherein the test circuit also uses the strength signal to indicate the second strength.

7. The semiconductor chip of claim 5, further comprising a second external terminal for external input of the oscillating test signal.

8. The semiconductor chip of claim 7, further comprising a third external terminal for external output of the oscillating output signal output by the functional block during normal operation of the semiconductor chip, wherein:

the oscillating test signal is input through the second external terminal to the functional block when the test circuit detects the first signal strength; and

the oscillating test signal is input through the third external terminal to the test circuit when the test circuit detects the second signal strength.

9. The semiconductor chip of claim 7, wherein the test circuit receives the oscillating test signal via the second external terminal.

10. The semiconductor chip of claim 9, further comprising a first switch connected to the functional block, for selectively supplying the test circuit with the oscillating test signal input to the functional block and the oscillating output signal output from the functional block.

11. The semiconductor chip of claim 1, further comprising:

a fourth external terminal for external input of an adjustment signal; and

an adjustment circuit for storing information provided by the adjustment signal and adjusting the functional block according to the stored information.

12. The semiconductor chip of claim 1, wherein the functional block is a radio-frequency transmitting amplifier.

13. The semiconductor chip of claim 1, wherein the input circuit includes a second switch for selectively supplying the functional block with the oscillating test signal during testing of the functional block and with a modulated communication signal during normal operation of the semiconductor chip.

14. The semiconductor chip of claim 1, wherein the functional block includes at least one of a receiving low-noise amplifier, a mixer, and an intermediate-frequency filter.

19. The method of claim 10, wherein the method is repeated to test mutually identical functional blocks in each of a plurality of semiconductor chips on a semiconductor wafer.

15. A method of testing a semiconductor chip including a functional block that generates an oscillating output signal to perform a communication function, the method comprising:

supplying an oscillating test signal to the functional block, thereby causing the functional block to generate the oscillating output signal;

detecting a first strength, the first strength being a strength of the oscillating output signal generated by the functional block in response to input of the oscillating test signal, by using a test circuit disposed in the semiconductor chip, the test circuit also generating a strength signal indicating the first strength;

outputting the strength signal from the semiconductor chip to a test device; and

evaluating the strength signal in the test device to decide whether the functional block has an operating characteristic that falls within a specified range.

16. The method of claim 15, further comprising using the test circuit disposed in the semiconductor chip to detect a second strength, the second strength being a strength of the oscillating test signal, the strength signal also indicating the second strength, wherein:

evaluating the strength signal includes taking a difference between the first strength and the second strength.

17. The method of claim 15, further comprising adjusting the operating characteristic of the functional block if the operating characteristic does not fall within the specified range but falls within an adjustable range.

18. The method of claim 17, wherein adjusting the operating characteristic further comprises:

sending an adjustment signal from the test device to the semiconductor chip;

storing information provided by the adjustment signal in the semiconductor chip; and

using an adjustment circuit disposed in the semiconductor chip to adjust the functional block according to the stored information.