METHOD AND APPARATUS FOR CREATING AND MANAGING WAIVER DESCRIPTIONS FOR DESIGN VERIFICATION
First Claim
1. A method comprising:
- receiving a plurality of first checksums corresponding to respective first geometric element errors waived in association with a block of an integrated circuit design, the plurality of first checksums being based on a first version of at least one design verification rule;
receiving a second checksum corresponding to a second geometric element error associated with the block, the second checksum being based on a second version of the at least one design verification rule;
determining whether the second checksum corresponds to at least one of the plurality of first checksums; and
generating, if the second checksum does not correspond to at least one of the plurality of first checksums, a waiver request for the second geometric element error.
3 Assignments
0 Petitions
Accused Products
Abstract
Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.
15 Citations
20 Claims
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1. A method comprising:
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receiving a plurality of first checksums corresponding to respective first geometric element errors waived in association with a block of an integrated circuit design, the plurality of first checksums being based on a first version of at least one design verification rule; receiving a second checksum corresponding to a second geometric element error associated with the block, the second checksum being based on a second version of the at least one design verification rule; determining whether the second checksum corresponds to at least one of the plurality of first checksums; and generating, if the second checksum does not correspond to at least one of the plurality of first checksums, a waiver request for the second geometric element error. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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receiving a plurality of first checksums corresponding to respective first geometric element errors waived in association with a first version of a block of an integrated circuit design; receiving a second checksum corresponding to a second geometric element error waived in association with a second version of the block; determining whether the second checksum corresponds to at least one of the plurality of first checksums; and generating, if the second checksum does not correspond to at least one of the plurality of first checksums, a wavier request for the second geometric element error. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method comprising:
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analyzing, based on at least one design verification rule, layout data corresponding to an integrated circuit including a block of intellectual property having at least one geometric element; generating, if the at least one geometric element violates the at least one design verification rule, at least one geometric element error; comparing the at least one geometric element error with waiver information stored in association with a version of the block; and disregarding the at least one geometric element error if the at least one geometric element error corresponds to at least some of the waiver information. - View Dependent Claims (18, 19, 20)
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Specification