Interposer Testing Using Dummy Connections

• US 20120298410A1
• Filed: 05/27/2011
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Hsiang-Tai, Lin, Chih-Hsien, Hung, Wei-Sho
• Granted Patent: US 8,664,540 B2
• Time in Patent Office: Days
• US Class Current: 174/264
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part

Abstract

An interconnection component includes a substrate, and an active through-substrate via (TSV) penetrating through the substrate. Active metal connections are formed over the substrate and electrically connected to the active TSV. At least one of a dummy pad and a dummy solder bump are formed at surfaces of the interconnection component. The dummy pad is over the substrate and electrically connected to the active TSV and the active metal connections. The dummy solder bump is under the substrate and electrically connected to the active metal connections. The dummy pad and the dummy solder bump are open ended.

Claims

1. A circuit structure comprising:

an interconnection component comprising;

a substrate;

an active through-substrate via (TSV) penetrating through the substrate;

active metal connections over the substrate and electrically connected to the active TSV; and

at least one of a dummy pad and a dummy solder bump at surfaces of the interconnection component, wherein the dummy pad is over the substrate and electrically connected to the active TSV and the active metal connections, wherein the dummy solder bump is under the substrate and electrically connected to the active metal connections, and wherein the dummy pad and the dummy solder bump are open ended.

2. The circuit structure of claim 1, wherein the interconnection component comprises the dummy pad.

3. The circuit structure of claim 2 further comprising a package component bonded to the interconnection component, wherein the package component and the dummy pad are on a same side of the interconnection component, and wherein the package component does not cover the dummy pad.

4. The circuit structure of claim 1 further comprising a package component bonded to the interconnection component, wherein the package component and the dummy solder bump are on a same side of the interconnection component, wherein the interconnection component comprises the dummy solder bump physically located between the substrate of the interconnection component and the package component, and wherein the dummy solder bump is not electrically connected to any conductive feature in the package component.

5. The circuit structure of claim 4 further comprising a dummy TSV in the substrate and electrically connected between the dummy solder bump and the active metal connections.

6. The circuit structure of claim 4 further comprising:

a dummy redistribution line (RDL) electrically connecting the dummy solder bump to the active TSV, wherein the dummy RDL and the active metal connections are on opposite sides of the substrate.

7. The circuit structure of claim 1, wherein the at least one of the dummy pad and the dummy solder bump is configured not be able to conduct any current through the at least one of the dummy pad and the dummy solder bump at a state when the circuit structure is powered on.

8. The circuit structure of claim 1, wherein the interconnection component comprises the dummy pad, and does not comprise the dummy solder bump, and wherein the interconnection component further comprises:

a dummy TSV in the substrate, wherein the substrate is a semiconductor substrate;

heavily doped regions in the substrate, wherein each of the active TSV and the dummy TSV is electrically connected to one of the heavily doped regions; and

an additional dummy pad electrically connected to the dummy TSV.

9. A circuit structure comprising:

an interposer free from active devices formed therein, wherein the interposer comprises;

a substrate;

an active through-substrate via (TSV) and a dummy TSV penetrating through the substrate;

active metal connections electrically interconnecting the active TSV and the dummy TSV;

a dummy pad configured to be used as a probe pad on a first surface of the substrate, wherein the dummy pad is electrically connected to the active metal connections; and

a dummy solder bump on a second surface of the substrate and electrically connected to the active TSV and the active metal connections, wherein the dummy pad and the dummy solder bump are on opposite surfaces of the interposer;

a first package component bonded to the first surface of the interposer; and

a second package component bonded to the second surface of the interposer, wherein the dummy solder bump is between the interposer and the second package component, and is not electrically connected to conductive features inside the package component.

10. The circuit structure of claim 9, wherein the first package component is smaller in size than the interposer, and wherein the dummy pad is not covered by the first package component.

11. The circuit structure of claim 10 further comprising a molding compound directly over and contacting the dummy pad.

12. The circuit structure of claim 11 further comprising:

a dummy redistribution line (RDL) electrically connecting the dummy solder bump to the active TSV, wherein the dummy RDL and the active metal connections are on opposite sides of the substrate.

13. The circuit structure of claim 11 further comprising:

a dummy TSV in the substrate and electrically connected between the active metal connections and the dummy solder bump.

14. A method comprising:

forming an interposer comprising;

forming an active through-substrate via (TSV) in a substrate of the interposer;

forming metal connections over and electrically connected to the active TSV;

forming a dummy pad electrically connected to the metal connections; and

forming a dummy solder bump electrically connected to the metal connections, wherein the dummy solder bump and the dummy pad are on opposite sides of the substrate; and

performing a first probing on one of the dummy pad and the dummy solder bump to find defect connections in the interposer.

15. The method of claim 14 further comprising bonding a first package component to the interposer, wherein the first package component and the dummy solder bump are on opposite sides of the substrate, and wherein the step of the first probing is performed after the step of bonding.

16. The method of claim 15 further comprising applying a molding compound on the package component, wherein the dummy pad is open ended after the molding compound is applied.

17. The method of claim 14 further comprising, after the step of the first probing, bonding a second package component to the interposer, wherein the dummy solder bump is between the substrate and the second package component, and wherein the dummy solder bump is open ended after the step of bonding.

18. The method of claim 14 further comprising forming a dummy TSV in the substrate and connected between the metal connections and the dummy solder bump.

19. The method of claim 14 further comprising forming a redistribution line (RDL), wherein the metal connections and the RDL are on opposite sides of the substrate, and wherein the RDL interconnects the metal connections and the dummy solder bump.

20. The method of claim 14 further comprising:

forming a dummy TSV in the substrate;

forming heavily doped regions in the substrate and electrically connected to the active TSV and the dummy TSV;

performing a second probing using the dummy pad, and using an additional dummy pad connected to the dummy TSV; and

after the step of performing the second probing, performing a grinding to remove the heavily doped regions from the substrate.