High-Gain Complementary Inverter with Ambipolar Thin Film Transistors and Fabrication Thereof

• US 20120298982A1
• Filed: 08/01/2011
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: National Chiao Tung University (Government of The Republic of China)
• Original Assignee: National Chiao Tung University (Government of The Republic of China)
• Inventors: Liu, Po-Tsun, Shieh, Han-Ping, Chou, Yi-Teh, Teng, Li-Feng, Fu, Chur-Shyang
• Granted Patent: US 8,563,974 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 19/20 comprising components having an active region that includes an inorganic semiconductor
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene

Abstract

The present invention relates to a high gain complementary inverter with ambipolar thin film transistors and fabrication thereof, comprising: a gate layer, a silica layer, a first active layer, a first source, a first drain, a second active layer, a second source and a second drain for fabrication cost and complexity reduction.

Claims

1. An ambipolar thin film transistor, comprising:

a gate layer, wherein material of the gate layer is low-resistivity Si or metal conductor;

a silica layer, forming on the gate layer;

an active layer, forming on the silica layer, wherein the active layer is formed by stacking up a n-type semiconductor thin film and a p-type semiconductor thin film;

a source, forming on the gate layer and connecting to one side of the active layer; and

a drain, forming on the gate layer, connecting to another side of the active layer and corresponding to the source.

2. The ambipolar thin film transistor of claim 1, wherein the metal conductor is aluminum (Al), molybdenum (Mo), titanium (Ti), wolfram (W) or the related alloys.

3. The ambipolar thin film transistor of claim 1, wherein material of the n-type semiconductor thin film is an amorphous oxide semiconductor.

4. The ambipolar thin film transistor of claim 1, wherein material of the n-type semiconductor thin film is an amorphous InGaZnO (a-IGZO), amorphous InZnO (a-IZO), amorphous AlZnTinO (a-AZTO) or amorphous HfInZnO (a-HIZO) or amorphous SiInZnO (a-SIZO) or amorphous ZnTinO (a-ZTO) or amorphous ZrZnTinO (a-ZrZTO).

5. The ambipolar thin film transistor of claim 1, wherein material of the p-type semiconductor thin film is pentacene or 3-hexylthiophene (P3HT).

6. The ambipolar thin film transistor of claim 1, wherein carrier concentration of the n-type semiconductor thin film is changed by changing temperature of the post thermal annealing so as to control the operation voltage, and wherein the temperature range is 150˜

650°

C.

7. A high gain complementary inverter with ambipolar thin film transistors, comprising:

a gate layer, wherein material of the gate layer is low-resistivity Si or metal conductor;

a silica layer, forming on the gate layer;

a first active layer, forming on the silica layer, wherein the active layer is formed by stacking up a first n-type semiconductor thin film and a first p-type semiconductor thin film;

a first source, forming on the gate layer and connecting to one side of the first active layer;

a first drain, forming on the gate layer, connecting to another side of the first active layer and corresponding to the first source;

a second active layer, forming on the silica layer, wherein the second active layer is formed by stacking up a second n-type semiconductor thin film and a second p-type semiconductor thin film;

a second source, forming on the gate layer and connecting to one side of the second active layer; and

a second drain, forming on the gate layer, connecting to another side of the second active layer and corresponding to the second source.

8. The ambipolar thin film transistor of claim 7, wherein the metal conductor is aluminum (Al), molybdenum (Mo), titanium (Ti), wolfram (W) or the related alloys.

9. The ambipolar thin film transistor of claim 7, wherein material of the first and second n-type semiconductor thin films are amorphous oxide semiconductors.

10. The ambipolar thin film transistor of claim 7, wherein material of the n-type semiconductor thin film is an amorphous InGaZnO (a-IGZO), amorphous InZnO (a-IZO), amorphous AlZnTinO (a-AZTO) or amorphous HfInZnO (a-HIZO) or amorphous SiInZnO (a-SIZO) or amorphous ZnTinO (a-ZTO) or amorphous ZrZnTinO (a-ZrZTO).

11. The ambipolar thin film transistor of claim 7, wherein material of the first and second p-type semiconductors thin film are pentacene or 3-hexylthiophene (P3HT).

12. The ambipolar thin film transistor of claim 7, wherein carrier concentration of the n-type semiconductor thin film is changed by changing temperature of the post thermal annealing so as to control the operation voltage, and wherein the temperature range is 150˜

650°

C.