NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20120299076A1
• Filed: 11/25/2011
• Published: 11/29/2012
• Est. Priority Date: 05/26/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YOO, Hyun-Seung, Choi, Eun-Seok
• Granted Patent: US 8,637,913 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.

Claims

1. A nonvolatile memory device comprising:

a channel vertically extending from a substrate, wherein the channel comprises a first region that is doped with first impurities and a second region that is disposed under the first region;

a plurality of memory cells and a selection transistor stacked over the substrate along the channel; and

a diffusion barrier interposed between the first region and the second region,

wherein a density of the first impurities is higher than a density of impurities of the second region.

2. The nonvolatile memory device of claim 1, wherein the diffusion barrier covers a side of the first region.

3. The nonvolatile memory device of claim 1, wherein the diffusion barrier is formed of a conductive material.

4. The nonvolatile memory device of claim 1, wherein the diffusion barrier is formed of a dielectric material with a thickness capable of tunneling of charges.

5. The nonvolatile memory device of claim 1, wherein the first region is formed of polysilicon.

6. The nonvolatile memory device of claim 1, wherein the first impurities are n-type impurities.

7. The nonvolatile memory device of claim 1, wherein a lower surface of the first region is higher than an upper surface of a gate of the selection transistor,

8. The nonvolatile memory device of claim 1, wherein a lower surface of the first region is same as an upper surface of a gate of the selection transistor or is lower than the upper surface of the gate of the selection transistor and higher than a lower surface of the gate of the selection transistor.

9. The nonvolatile memory device of claim 1,

wherein the channel includes a pair of channels, and

wherein the pair of channels are connected with each other by a connection channel that is disposed under lower ends of the pair of channels.

10. The nonvolatile memory device of claim 1, further comprising:

gate induced drain leakage occurring regions that extend from a drain side edge of a gate of the selection transistor to the diffusion barrier pattern.

11. A method for fabricating a nonvolatile memory device, comprising:

stacking a plurality of memory cells and a selection transistor along a channel that vertically extends from a substrate ;

forming a trench by removing an upper portion of the channel;

forming a diffusion barrier over a bottom of the trench; and

forming a semiconductor pattern doped with first impurities over the diffusion barrier in the trench,

wherein a density of the first impurities is higher than a density of impurities of the channel.

12. The method of claim 11, wherein the diffusion barrier is additionally formed on a sidewall of the trench.

13. The method of claim 11, wherein the forming of the diffusion barrier and the semiconductor pattern comprises:

forming a diffusion barrier layer on an entire surface of a structure including the trench;

forming a semiconductor layer which is doped with the first impurities over the diffusion barrier layer; and

performing a planarization process until an upper surface of a structure comprising the plurality of memory cells and the selection transistor is exposed.

14. The method of claim 11, wherein the diffusion barrier is formed of a conductive material.

15. The method of claim 11, wherein the diffusion barrier is formed of a dielectric material with a thickness capable of tunneling of charges.

16. The method of claim 11, wherein the forming of the trench is implemented such that the bottom of the trench is higher than an upper surface of a gate of the selection transistor.

17. The method of claim 11, wherein the forming of the trench is implemented such that the bottom of the trench is same as an upper surface of a gate of the selection transistor or is lower than the upper surface of the gate of the selection transistor and higher than a lower surface of the gate of the selection transistor.

18. The method of claim 11, wherein the first impurities are n-type impurities.

19. The method of claim 11,

wherein the channel includes a pair of channels, and

wherein the pair of channels are connected with each other by a connection channel which is disposed under lower ends of the pair of channels.