SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20120299084A1
• Filed: 05/21/2012
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TOBA, Koichi, SAITO, Kentaro, YANAGISAWA, Kazumasa, ISHII, Yasushi
• Granted Patent: US 9,159,843 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

first gate electrode formed in an upper part of the semiconductor substrate;

a second gate electrode that is formed in an upper part of the semiconductor substrate and is adjacent to the first gate electrode;

a first insulating film formed between the first gate electrode and the semiconductor substrate; and

a second insulating film that is formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode, and that includes an electric charge accumulation part, wherein;

the second gate electrode has a first metal film adjacent to the second insulating film and a first silicon film that is formed over the first metal film and is separated from the second insulating film via the first metal film; and

a first metal oxide portion is formed in an upper end part of the first metal film.

2. The semiconductor device according to claim 1, wherein a metal element constituting the first metal oxide portion and a metal element constituting the first metal film are the same.

3. The semiconductor device according to claim 2, wherein the first metal oxide portion is formed by oxidation of a part of the first metal film.

4. The semiconductor device according to claim 3, wherein a first metal silicide layer is formed in an upper part of the first silicon film.

5. The semiconductor device according to claim 4, wherein a second metal silicide layer is formed in an upper part of the first gate electrode.

6. The semiconductor device according to claim 5, wherein:

the semiconductor device has a nonvolatile memory; and

the first and second gate electrodes are gate electrodes constituting the nonvolatile memory.

7. The semiconductor device according to claim 6, wherein:

a sidewall spacer is formed over a side wall that is a side wall of the second gate electrode and that is on a side opposite to the side adjacent to the first gate electrode; and

a second metal oxide portion is formed between an end part located on an opposite side of the upper end part of the first metal film and the sidewall spacer.

8. The semiconductor device according to claim 7, wherein at least apart of the second metal oxide portion is located between the first silicon film and the second insulating film.

9. The semiconductor device according to claim 8, wherein the second metal oxide portion is formed by oxidation of a part of the first metal film.

10. The semiconductor device according to claim 9, wherein the first gate electrode has a second metal film formed over the first insulating film, and a second silicon film formed over the second metal film, and the second metal silicide layer is formed in an upper part of the second silicon film.

11. The semiconductor device according to claim 10, wherein the first insulating film is a high-permittivity film.

12. The semiconductor device according to claim 11, wherein impurity concentration in a channel region below the first gate electrode in the semiconductor substrate is not more than 1×

10¹⁷/cm³.

13. A semiconductor device, comprising:

a semiconductor substrate;

a first gate electrode formed in an upper part of the semiconductor substrate;

a second gate electrode that is formed in an upper part of the semiconductor substrate and is adjacent to the first gate electrode;

a first insulating film formed between the first gate electrode and the semiconductor substrate;

a second insulating film that is formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode, and that includes an electric charge accumulation part, wherein the first gate electrode has a metal film formed over the first insulating film.

14. The semiconductor device according to claim 13, wherein the first gate electrode further has a silicon film formed over the metal film.

15. The semiconductor device according to claim 14, wherein the first insulating film is a high-permittivity film.

16. The semiconductor device according to claim 15, wherein impurity concentration in a channel region below the first gate electrode in the semiconductor substrate is not more than 1×

10¹⁷/cm³.

17. The semiconductor device according to claim 16, wherein:

the semiconductor device has a nonvolatile memory; and

the first and second gate electrodes are gate electrodes constituting the nonvolatile memory.

18. The semiconductor device according to claim 17, wherein an end part of the metal film in a gate length direction of the first gate electrode is oxidized.

19. A method of manufacturing a semiconductor device having:

a semiconductor substrate;

a first gate electrode and a second gate electrode that are formed in an upper part of the semiconductor substrate and are adjacent to each other;

a first gate insulating film formed between the first gate electrode and the semiconductor substrate; and

a second gate insulating film that is formed between the second gate electrode and the semiconductor substrate and that has an electric charge accumulation part therein, the method comprising the steps of;

(a) providing the semiconductor substrate;

(b) forming a first insulating film for the first gate insulating film on a main surface of the semiconductor substrate;

(c) forming a first conductor film for the first gate electrode over the first insulating film;

(d) patterning the first conductor film to form the first gate electrode;

(e) forming a second insulating film that is for the second gate insulating film and that includes an electric charge accumulation part, on a main surface of the semiconductor substrate and on a surface of the first gate electrode;

(f) forming a first metal film over the second insulating film;

(g) forming a first silicon film over the first metal film;

(h) etching-back a stacked film of the first silicon film and the first metal film to leave the stacked film over a side wall of the first gate electrode via the second insulating film, and to form the second gate electrode;

(i) removing the second insulating film in a portion not covered with the second gate electrode to leave the second insulating film between the second gate electrode and the semiconductor substrate, and between the first gate electrode and the second gate electrode; and

(j) oxidizing an upper end part of the first metal film exposed from an upper surface of the second gate electrode to form a first metal oxide portion.

20. The method of manufacturing a semiconductor device according to claim 19, further comprising the steps of:

(k) forming a third insulating film to cover the first and second gate electrodes over the semiconductor substrate; and

(l) etching-back the third insulating film to leave the third insulating film over side walls of the first and second gate electrodes on sides opposite to sides adjacent to each other, and to form a sidewall spacer, wherein;

the third insulating film formed in the step (k) includes a single film of a first silicon oxide film, or a stacked film having the first silicon oxide film as the lowermost layer; and

in the step (j), an upper end part of the first metal film is oxidized in forming the first silicon oxide film to form the first metal oxide portion.

21. The method of manufacturing a semiconductor device according to claim 20, wherein, in the step (j), a end part that is located on a side opposite to the upper end part of the first metal film and that is exposed from a side wall on a side opposite to a side adjacent to the first gate electrode of the second gate electrode is oxidized to form a second metal oxide portion.

22. The method of manufacturing a semiconductor device according to claim 21, further comprising the step of, after the step (l), (m) forming a metal silicide layer in an upper part of the first silicon film constituting the second gate electrode and in that of the first gate electrode.

23. The method of manufacturing a semiconductor device according to claim 19, further comprising the steps of, after the step (i) and before the step (j):

(i1) forming a silicon nitride film to cover the first and second gate electrodes over the semiconductor substrate; and

(i2) etching-back the silicon nitride film to leave the silicon nitride film over side walls of the first and second gate electrodes on sides opposite to sides adjacent to each other, and to expose an upper end part of the first metal film from an upper surface of the second gate electrode.