Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods

• US 20120299090A1
• Filed: 11/17/2011
• Published: 11/29/2012
• Est. Priority Date: 05/25/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ji-Young, Jin, Gyo-Young, Hong, Hyeong-Sun, Oh, Yong-Chul, Hwang, Yoo-Sang, Woo, Dong-Soo, Chung, Hyun-Woo, Choi, Sung-Kwan
• Granted Patent: US 8,884,340 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Claims

1. A semiconductor device comprising:

a semiconductor substrate including first and second spaced apart source/drain regions defining a channel region therebetween;

a control gate structure on the channel region between the first and second spaced apart source/drain regions, wherein the control gate structure includes,

a first gate electrode on the channel region adjacent the first source/drain region, and

a second gate electrode on the channel region adjacent the second source/drain region, wherein the first and second gate electrodes are electrically isolated.

2. The semiconductor device of claim 1 wherein at least a portion of the first gate electrode on the channel region is spaced apart from the second source/drain region, and wherein at least a portion of the second gate electrode on the channel region is spaced apart from the first source/drain region

3. The semiconductor device of claim 1 wherein the control gate structure further includes a gate insulator structure between the first gate electrode and the channel region and between the second gate electrode and the channel region.

4. The semiconductor device of claim 3 wherein the gate insulator structure further includes,

a first gate insulator between the first gate electrode and the channel region, and

a second gate insulator between the second gate electrode and the channel region,

wherein at least one of the first and second gate insulators extends between the first and second gate electrodes.

5. The semiconductor device of claim 1 wherein the semiconductor substrate further includes third and fourth spaced apart source/drain regions defining a second channel therebetween and an isolation layer separating the first and second channel regions, and wherein the first and second gate electrodes extend from the first channel region across the isolation layer to the second channel region.

6. The semiconductor device of claim 1 wherein the semiconductor substrate further comprises a third source/drain region spaced apart from the first source/drain region and defining a second channel region between the first and third source/drain regions, wherein the semiconductor device further comprises:

a second control gate structure on the second channel region between the first and third spaced apart source/drain regions, wherein the second control gate structure includes,

a third gate electrode on the second channel region adjacent the first source/drain region, and

a fourth gate electrode on the second channel region adjacent the third source/drain region, wherein the third and fourth gate electrodes are electrically isolated.

7. The semiconductor device of claim 1 further comprising:

a bit line coupled to the first source/drain region; and

a memory storage element coupled to the second source/drain region.

8. The semiconductor device of claim 1 wherein the first and second source/drain regions and the channel region are provided on a planar surface of the semiconductor substrate.

9. The semiconductor device of claim 1 wherein the semiconductor substrate includes a trench in a surface thereof, wherein the first and second gate electrodes are provided adjacent a sidewall of the trench, and wherein the second gate electrode is between the first gate electrode and the surface of the semiconductor substrate.

10. The semiconductor device of claim 9 wherein the first and second source/drain regions are provided at the surface of the semiconductor substrate on opposite sides of the trench, wherein the second gate electrode is between portions of the first and second source/drain regions, wherein the first gate electrode is adjacent portions of the first source/drain region, and wherein the first gate electrode is spaced apart from the second source/drain electrode.

11. The semiconductor device of claim 10 wherein a depth that the first source/drain region extends into the semiconductor substrate is greater than a depth that the second source/drain region extends into the substrate.

12. The semiconductor device of claim 9 wherein the trench includes first and second sidewalls and a bottom surface between the first and second sidewalls, wherein the first source/drain region is adjacent the bottom surface of the trench, wherein the second source/drain region is adjacent the first sidewall, and wherein portions of each of the first and second gate electrodes are provided in the trench along the first sidewall between the first and second source/drain electrodes.

13. The semiconductor device of claim 12 wherein the semiconductor substrate further includes a third source/drain region adjacent the second sidewall of the trench and spaced apart from the first source/drain region, and wherein the first and third source/drain regions define a second channel region therebetween, the semiconductor substrate further comprising:

a second control gate structure in the trench on the second channel region between the first and third spaced apart source/drain regions, wherein the second control gate structure includes,

a third gate electrode on the second channel region adjacent the first source/drain region, and

a fourth gate electrode on the second channel region adjacent the third source/drain region, wherein the third and fourth gate electrodes are electrically isolated.

14. The semiconductor device of claim 13 further comprising:

a bit line contact coupled to the first source/drain region, wherein the bit line contact extends through the trench between the first and third gate electrodes and between the second and fourth gate electrodes;

a bit line electrically coupled to the first source/drain region through the bit line contact;

a first memory storage element coupled to the second source/drain region; and

a second memory storage element coupled to the third source/drain region.

15. The semiconductor device of claim 9 wherein at least one of the first and/or second source/drain regions has a width in a direction parallel to the surface of the substrate that is in the range of about 5 nanometers to about 20 nanometers.

16. The semiconductor device of claim 9 wherein the second source/drain region has a first width in a direction parallel to the surface of the substrate, the semiconductor device further comprising:

a conductive pad on the second source/drain region and electrically coupled thereto, wherein the conductive pad has a second width in the direction parallel to the surface of the substrate, wherein the second width is greater than the first width.

17. The semiconductor device of claim 1 further comprising:

a controller electrically coupled to the first and second gate electrodes, wherein the controller is configured to apply different first and second voltages to the first and second gate electrodes to block electrical current flow through the channel region between the first and second source/drain regions.

18. The semiconductor device of claim 17 wherein the second voltage is greater than the first voltage.

19. The semiconductor device of claim 17 wherein the first voltage is less than a ground voltage of the semiconductor device and wherein the second voltage is greater than the ground voltage of the semiconductor device.

20-35. -35. (canceled)

36. A semiconductor device comprising:

a semiconductor substrate including a trench in the semiconductor substrate and including first and second source/drain regions on opposite sides of the trench defining a channel region through portions of the semiconductor substrate adjacent the trench between the first and second source/drain regions; and

a control gate structure in the trench, wherein the control gate structure includes first and second gate electrodes on the channel region in the trench, wherein the second gate electrode is between the first gate electrode and the surface of the substrate, wherein the first and second gate electrodes are electrically isolated.

37-47. -47. (canceled)