Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected Through Conductive Vias Formed in Encapsulant Around Die

• US 20120299191A1
• Filed: 05/26/2011
• Published: 11/29/2012
• Est. Priority Date: 05/26/2011
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Camacho, Zigmund R.
• Granted Patent: US 8,389,333 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24105 Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/245 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82031 : by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

Claims

1. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing a first encapsulant around the first semiconductor die;

forming a first conductive layer over the first semiconductor die and first encapsulant;

disposing a second semiconductor die over the first conductive layer;

depositing a second encapsulant around the second semiconductor die while exposing a surface of the second semiconductor die including a contact pad;

forming a second conductive layer over the second semiconductor die and second encapsulant electrically connected to a contact pad of the second semiconductor die; and

forming a plurality of conductive vias through the first and second conductive layers and through the first and second encapsulants electrically connected to the first and second conductive layers.

2. The method of claim 1, further including:

disposing a third semiconductor die over the second conductive layer;

depositing a third encapsulant around the third semiconductor die;

forming an insulating layer over the third semiconductor die and third encapsulant;

forming a third conductive layer over the insulating layer and third encapsulant electrically connected to a contact pad of the third semiconductor die; and

forming the plurality of conductive vias through the first, second, and third encapsulants outside a footprint of the first, second, and third semiconductor die electrically connected to the first, second, and third conductive layers.

3. The method of claim 2, further including forming a first interconnect structure over the second or third conductive layer electrically connected to the conductive vias.

4. The method of claim 3, further including forming a second interconnect structure over the first encapsulant electrically connected to the conductive vias.

5. The method of claim 4, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first and second interconnect structures and conductive vias.

6. The method of claim 1, wherein the first encapsulant includes a thickness different from the second encapsulant.

7. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a first conductive layer over the first semiconductor die;

disposing a second semiconductor die over the first semiconductor die;

forming a second conductive layer over the second semiconductor die electrically connected to a contact pad of the second semiconductor die; and

forming a plurality of conductive vias through the first and second conductive layers and outside a footprint of the first and second semiconductor die.

8. The method of claim 7, further including:

depositing a first encapsulant around the first semiconductor die;

forming a first insulating layer over the first semiconductor die and first encapsulant prior to forming the first conductive layer;

depositing a second encapsulant around the second semiconductor die; and

forming a second insulating layer over the second semiconductor die and second encapsulant prior to forming the second conductive layer.

9. The method of claim 8, further including:

disposing a third semiconductor die over the second semiconductor die;

depositing a third encapsulant around the third semiconductor die;

forming a third insulating layer over the third semiconductor die and third encapsulant;

forming a third conductive layer over the third insulating layer and third encapsulant electrically connected to a contact pad of the third semiconductor die; and

forming the plurality of conductive vias through the first, second, and third encapsulants outside a footprint of the first, second, and third semiconductor die electrically connected to the first, second, and third conductive layers.

10. The method of claim 9, further including forming an interconnect structure over the second or third semiconductor die electrically connected to the conductive vias.

11. The method of claim 8, further including forming an interconnect structure over the first encapsulant electrically connected to the conductive vias.

12. The method of claim 7, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the conductive vias.

13. The method of claim 8, wherein the first encapsulant includes a thickness different from the second encapsulant.

14. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing a first encapsulant around the first semiconductor die;

disposing a second semiconductor die over the first semiconductor die;

depositing a second encapsulant around the second semiconductor die to expose a surface of the second semiconductor die including a contact pad; and

forming a plurality of conductive vias through the first and second encapsulants.

15. The method of claim 14, further including:

forming a first insulating layer over the first semiconductor die and first encapsulant;

forming a first conductive layer over the first insulating layer and first encapsulant electrically connected to a contact pad of the first semiconductor die;

forming a second insulating layer over the second semiconductor die and second encapsulant;

forming a second conductive layer over the second insulating layer and second encapsulant electrically connected to a contact pad of the second semiconductor die; and

forming the plurality of conductive vias through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

16. The method of claim 15, further including:

disposing a third semiconductor die over the second semiconductor die;

depositing a third encapsulant around the third semiconductor die;

forming a third insulating layer over the third semiconductor die and third encapsulant;

forming a third conductive layer over the third insulating layer and third encapsulant electrically connected to a contact pad of the third semiconductor die; and

forming the plurality of conductive vias through the first, second, and third encapsulants outside a footprint of the first, second, and third semiconductor die electrically connected to the first, second, and third conductive layers.

17. The method of claim 16, further including forming an interconnect structure over the second or third semiconductor die electrically connected to the conductive vias.

18. The method of claim 14, further including forming an interconnect structure over the first encapsulant electrically connected to the conductive vias.

19. The method of claim 14, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the conductive vias.

20. The method of claim 14, wherein the first encapsulant includes a thickness different from the second encapsulant.

21. A semiconductor device, comprising:

a first semiconductor die;

a first conductive layer formed over the first semiconductor die and electrically connected to a contact pad of the first semiconductor die;

a second semiconductor die disposed over the first conductive layer;

a second conductive layer formed over the second semiconductor die and electrically connected to a contact pad of the second semiconductor die; and

a plurality of conductive vias formed through the first and second conductive layers outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

22. The semiconductor device of claim 21, further including:

a first encapsulant deposited around the first semiconductor die;

a second encapsulant deposited around the second semiconductor die;

a third semiconductor die disposed over the second semiconductor die;

a third encapsulant deposited around the third semiconductor die;

an insulating layer formed over the third semiconductor die and third encapsulant;

a third conductive layer formed over the insulating layer and electrically connected to a contact pad of the third semiconductor die; and

the plurality of conductive vias formed through the first, second, and third encapsulants outside a footprint of the first, second, and third semiconductor die electrically connected to the first, second, and third conductive layers.

23. The semiconductor device of claim 21, further including forming an interconnect structure over the second or third semiconductor die electrically connected to the conductive vias.

24. The semiconductor device of claim 22, further including forming an interconnect structure over the first encapsulant electrically connected to the conductive vias.

25. The semiconductor device of claim 21, further including a plurality of stacked semiconductor devices electrically connected through the conductive vias.